Browsing by Subject "Random access memory"
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Item Central processing unit built-in self-test for random access memory test and repair(Texas Tech University, 2002-05) Wrights, Nathan W.Digital signal processor integrated circuits dedicate a significant percentage of the die area to embedded static random access memory, and by designing redundant elements into the memory, repairs to the memory as an effective way to increase digital signal processor functional yields. A time and resource efficient test has been developed to find the memory defects and to determine if a repair solution is available to bypass the memory defects. In this paper, the development of a central processing unit built-in selftest for test and repair of redundant random access memory is examined and conclusions are drawn about its tunctionality. A discussion of several possible test methods is included along with an explanation for the selection of a central processing unit built-in self-test. Specific portions of the test are examined in detail, including the development of the repair algorithm and the creation of a compressed enhanced software defect analysis image. The results developed in this paper demonstrate that a central processing unit built-in self-test is an effective solution for the test and repair a static random access memory.Item High performance PCI-compatible DDR SDRAM controller and inter-processor logic design for quad-DSP board(Texas Tech University, 2004-08) Mane, Amitkumar TulshidasThe focus of this thesis is on the logic design needed for Quadia, a signal processing board developed at Innovative Integration, Inc. Quadia is an ideal platform for integrating high performance DSPs and I/O technologies into advanced signal processing, data acquisition and real-time applications such as telecom, RADAR, SONAR and wireless communications. The logic design developed in this thesis for Quadia includes a Global Memory Pool Controller and an Inter-processor FIFO Mesh. The Global Memory Pool Controller provides access to a 512 Mbit Global Memory Pool over the PCI bus. Quadia is a multi-processor board, and inter-processor communication is the most crucial aspect of this design. The inter-processor FIFO Mesh provides extreme flexibility and low latency for very complex exchanges of bulk data and control messages between DSPs. Each DSP on the board has a private link mapped to its EMIF-B. Using this FIFO Mesh, user software can implement DMA-driven packet-based inter-processor communication. All the logic needed for this board is implemented in a Xilinx FPGA, the VirtexII-Pro XC2VP20.Item Qualification of the assembly process of flip-chip BGA packages for the next generation synchronous quad data rate sram device to ensure reliability(2012-05) Shivan, Nivetha; Gale, Richard O.; Bayne, Stephen B.Quad Data Rate SRAMS (QDR SRAM) with a maximum speed of 550MHz are the latest technology QDRs in the market. These devices use the traditional wire-bonding interconnects ball grid array package technology with about 165 signal pins. There are next generation QDR SRAMS that are being designed which operates at speeds much higher than 550MHz and signal pins twice as much as that of the present QDRs. These new products would require a new packaging interconnect technology called Flip Chip in order to accommodate higher speed and increased number of signal pins. The reason for this is that Flip Chip shows improved electrical properties over wire-bonding technologies. In this thesis, we deal with the qualification of Flip Chip interconnects technology for a higher pin count device.