Central processing unit built-in self-test for random access memory test and repair



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Texas Tech University


Digital signal processor integrated circuits dedicate a significant percentage of the die area to embedded static random access memory, and by designing redundant elements into the memory, repairs to the memory as an effective way to increase digital signal processor functional yields. A time and resource efficient test has been developed to find the memory defects and to determine if a repair solution is available to bypass the memory defects. In this paper, the development of a central processing unit built-in selftest for test and repair of redundant random access memory is examined and conclusions are drawn about its tunctionality. A discussion of several possible test methods is included along with an explanation for the selection of a central processing unit built-in self-test. Specific portions of the test are examined in detail, including the development of the repair algorithm and the creation of a compressed enhanced software defect analysis image. The results developed in this paper demonstrate that a central processing unit built-in self-test is an effective solution for the test and repair a static random access memory.