High performance PCI-compatible DDR SDRAM controller and inter-processor logic design for quad-DSP board

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Texas Tech University

The focus of this thesis is on the logic design needed for Quadia, a signal processing board developed at Innovative Integration, Inc. Quadia is an ideal platform for integrating high performance DSPs and I/O technologies into advanced signal processing, data acquisition and real-time applications such as telecom, RADAR, SONAR and wireless communications. The logic design developed in this thesis for Quadia includes a Global Memory Pool Controller and an Inter-processor FIFO Mesh. The Global Memory Pool Controller provides access to a 512 Mbit Global Memory Pool over the PCI bus. Quadia is a multi-processor board, and inter-processor communication is the most crucial aspect of this design. The inter-processor FIFO Mesh provides extreme flexibility and low latency for very complex exchanges of bulk data and control messages between DSPs. Each DSP on the board has a private link mapped to its EMIF-B. Using this FIFO Mesh, user software can implement DMA-driven packet-based inter-processor communication. All the logic needed for this board is implemented in a Xilinx FPGA, the VirtexII-Pro XC2VP20.