Browsing by Subject "Integrated circuits"
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Item A VLSI optical detector array employing heterodyne detection(Texas Tech University, 1997-05) Soni, Tejvansh SinghThe integration of image sensors with circuitry for driving the image sensor and performing on-chip signal processing is becoming increasingly popular for a multitude of signal processing applications. A high degree of on-chip signal processing helps enable miniaturization of instrument systems and simplify system interfaces. In this work, the design of a powerful and versatile VLSI optical sensor array, with on-chip circuitry to perform temporal electronic heterodyne detection on a pixel-bypixel basis is presented. Heterodyne detection techniques significantly enhance the dynamic range and signal to noise ratio, as compared to base-band detectors. The unavailability of heterodyne detector arrays has been a bottleneck in many imageprocessing systems, restricting the use of heterodyne detection techniques to scanning based systems, or systems having a single temporal output, such as acousto-optic space integrating correlators and convolvers. The need for heterodyne detector arrays in acousto-optics has been emphasized by prominent researchers in the field.Item Algorithms for circuit layout compaction of building blocks(Texas Tech University, 1985-12) Varadarajan, RamachandranCompaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce error free IC layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced by minimizing the pitch in each dimension separately. The algorithm is capable of handling mixed constraints; i.e., the constraints arising from design rule requirements (lower-bound type), and the User defined constraints (equality and upper-bound type).Item An efficient algorithm for switchbox routing(Texas Tech University, 1983-08) Tsay, Ching-yuhNot availableItem Automation of semiconductor processing equipment(Texas Tech University, 1999-08) Vuppaladadium, VijayThis thesis describes a methodology to Automate Semiconductor Fabrication Equipment. The current processing Industry makes use of stand-alone equipment with built-in Microcontrollers, which are hardcoded or programmed using EPROMs to accomplish that particular process. The cost of building such systems is expensive. Automation of these systems is time consuming and difficult. These systems require a lot of user intervention during processing. This thesis presents a comprehensive insight into a generic approach of Automation of a process. A methodology has been discussed to automate a machine using DAQ (Data Acquisition Boards) and Extemal Interface Boards controlled by LabVTEW, a graphical programming language tool. This approach of automation is implemented and verified on two processing systems, namely a Plasma Etcher and a Plasma Deposition System. The project explains the specifications of the hardware needed and describes a modular approach to design the LabVIEW control program. It explains how this approach can achieve improved process performance by efficient monitoring and controlling of the process parameters for increased yield and productivity. The advantages of this methodology of automation are discussed along with applications.Item Central processing unit built-in self-test for random access memory test and repair(Texas Tech University, 2002-05) Wrights, Nathan W.Digital signal processor integrated circuits dedicate a significant percentage of the die area to embedded static random access memory, and by designing redundant elements into the memory, repairs to the memory as an effective way to increase digital signal processor functional yields. A time and resource efficient test has been developed to find the memory defects and to determine if a repair solution is available to bypass the memory defects. In this paper, the development of a central processing unit built-in selftest for test and repair of redundant random access memory is examined and conclusions are drawn about its tunctionality. A discussion of several possible test methods is included along with an explanation for the selection of a central processing unit built-in self-test. Specific portions of the test are examined in detail, including the development of the repair algorithm and the creation of a compressed enhanced software defect analysis image. The results developed in this paper demonstrate that a central processing unit built-in self-test is an effective solution for the test and repair a static random access memory.Item CMOS modular register file for CPU design(Texas Tech University, 2000-05) Gu, XiaowuFrom the above discussion, the building block-pased design is one of the top choices in present integrated circuit design world. By using basic building blocks, largescale digital design can achieve lower cost, higher speed, higher reliability, shorter design time and flexibility. Currently, to invesfigate the nature and advantages of building block design, a tool library with various functional building blocks in layout form is being designed in our research group. In addition, in the near future, some microprocessors will be built up by connecting those powerful, fast, expandable and flexible functional building blocks together as design examples of the building block-based design method. A basic microprocessor has a timing and control unit for sequencing, an arithmetic logic unit (ALU) for processing instmctions, an instmction decoder, and register banks for temporary storage during arithmetic operation. Figure 1.1 [2] shows a diagram of a basic microprocessor.Item Design of algorithm transformations for VLSI array processing(Texas Tech University, 1986-12) Dorairaj, RavishankarThe rapid advances in the very large scale integrated (VLSI) technology has created a flurry of research in designing future computer architectures. Many methods have been developed for parallel processing of algorithms by directly mapping them onto parallel architectures. A procedure, based on the mathematical transformation of the index set and dependence vectors of an algorithm, is developed to find algorithm transformations for VLSI array processing. The algorithm is modeled as a program graph which is a directed graph. Techniques are suggested to regularize the data-flou in an algorithm, thereby minimizing the communication requirements of the architecture. We derive a set of sufficient conditions on the structure of data-flou of a class of algorithms, for the existence of valid transformations. The VLSI array is modeled as a directed graph, and the program graph is mapped onto this using the algorithm transformation.Item Design of multiplier and its VLSI implementation(Texas Tech University, 1999-05) Liu, QiA 3-bit recoding algorithm is used to implement a parallel multiplier in two's complement. The circuits at gate level for implementing 8 x 8-bit multiplier are presented. To obtain highest speed, (1) carry skip adders combined with carry select adders are adopted to implement two's complement multiplier, (2) carry save adders combined with carry select adders are used to add partial products. An 8x8-bit multiplier was implemented physically with 1.2^m CMOS SCN (Scaleable N-well) technology using Tanner L-Edit CMOS layout tool. The area of the chip (not including pads frame) is 1 mm . The chip has been fabricated and tested. From the chip test, the execution time is less than 5.7ns. A 16x16-bit multiplier implemented with 8x8-bit multiplier cells using Pspice software tool was also presented. The execution time of the 16x16-bit multiplier is about 1.5 times that of the 8x 8-bit multiplier from the Pspice simulation.Item Die level sorting of an integrated circuit(Texas Tech University, 2000-12) Black, Kelley AnnThe semiconductor industry is one that relies heavily on the reliability of its products. However, the cost of developing reliable products can be considerably high. Expensive testing processes have inspired the companies to develop test reduction methods. One such method is die level sorting. Die level sorting uses wafer level testing to determine if a device will be a reliable product. This paper describes the approach to developing a die level sorting algorithm and then applies the method to develop an algorithm for a semiconductor integrated circuit.Item Digital logic testing and verification using ordered binary decision diagrams(Texas Tech University, 1995-05) Randhawa, Preet SinghComputer-Aided Design has become a major part of design and testing of digital circuits. Since CAD systems use Boolean expressions extensively for testing and verifying digital circuits, it is necessary to find an efficient data structure algorithms for the representation and manipulation of Boolean expressions. This paper investigates Ordered Binary Decision Diagrams and several ordering techniques to satisfy this need. The OBDD program was implemented and tested on ISCAS89 benchmark circuits. A translator was developed to convert the benchmark circuits into a format that could be read by the OBDD program. The effect of variable ordering on the size of the resulting graph was investigated. We implemented Depth First Traversal and Variable Interleaving algorithms for variable ordering. Furthermore, we developed two new variable ordering techniques, the Modified Depth First Traversal and the ordering given by the translator. The performance of these algorithms was compared to OBDDs produced by the original ordering (given in the ISCAS89 circuits) as well as by a random ordering. It was found that the ordering produced by the translator provided the smallest OBDDs overall.Item Dynamics of an electrostatically controlled bulk micromachined silicon torsion mirror in air(Texas Tech University, 2004-08) Gokarnesan, ManikandanStatic and dynamic characterizations of micromirrors are important to understand the mirror's responses for different inputs under various conditions. The characterizations are important not only to choose and operate a mirror for a particular end application but also to continuously provide feedback to the design and processing teams in a new mirror development. This feedback should include device behavior, system parameters, and material properties. The dynamic behavior of the mirrors is significant to implement adaptive control algorithms to precisely position the mirror. In this thesis, instrumentation techniques to measure the static and dynamic responses of a bulk micromachined Silicon torsion mirror have been developed. These measurements include tilt angle versus driving voltage curves and frequency response curves. Several important parameters, like the torsion spring constant, damping ratio, natural frequency, moment of inertia, and mass were estimated for the mirror. These parameters were incorporated in the mirror model to simulate the mirror responses. Agreement of the simulated and experimental results confirmed the validity of the measurement techniques. Effects of nonlinearity in the torsion springs resulted in deviations between the actual and the simulated mirror responses at higher voltages and at larger angles. The measured parameters were further used to simulate the dynamic responses, response to a step voltage, capacitance variations, and the dynamic deformations of the mirror. The various parameters estimated will be central to implementing feedback control algorithms to accurately position the mirror throughout the entire gap.Item Efficient algorithms for channel routing in circuit layout(Texas Tech University, 1983-08) Boar, Show-yuiNot availableItem Exposure of soft defects in integrated circuits using Taguchi methods(Texas Tech University, 2001-05) Towle, Christopher M.The work of Taguchi for determining the optimal settings of controllable factors through off-line experiments focuses on products with a single quality characteristic or response. However, most products have several quality characteristics or responses of interest. Taguchi's technique in itself optimizes a single response or performance characteristic yielding a set of process parameters. This particular setting may not give desired results for other characteristics of the product. In such cases, a need arises to obtain a single setting (optimal setting) of the process parameters, which can be used to produce the products with optimum or near optimum quality characteristics as a whole. Multi-characteristic response optimization may be the solution of the above problem. In the present paper a case study on frequency shift in a microprocessor is investigated utilizing a simplified multi-criterion methodology based on Taguchi's approach and utility concept, is discussed.Item Integrated circuit design of a sequential state machine(Texas Tech University, 1996-12) Venkataraman, Kamala NNot availableItem Modular design of a program control unit(Texas Tech University, 2000-08) Polepeddi, TaarinyaModular based design is used for flexibility, simplicity and to lower the cost and labor in designing general purpose or application specific digital circuits. This research investigates the nature and advantages of digital building blocks by implementing a modular based design, 8-bit Program control unit. The 8-bit Program Control Unit is designed using Logic Works 3.0.3, laid out using L-Edit(Version 7) and simulated in PSpice. This paper contains the design method, layout considerations and simulation results. It also discusses history, advantages and problems with digital building block.Item Modular microcontroller design(Texas Tech University, 1999-05) Abraham, Bobby K.Integrated Circuits (IC) have developed from its earliest forms of MSI, LSI level circuits to VLSI (Very Large- Scale Integration) and ULSI (Ultra Large- Scale Integration) circuits. Along with the rapid advancement in processing technology which made this possible, the complexity in design and design concerns increased. More time is consumed in designing a IC than producing it. As a result, the cost of design is a major concern. To minimize the effects of cost and time in producing an IC, the industry started adopting a "Design Reuse" concept. This is facilitated by modular design approach where the same design is reused for a new product. The whole digital system is realized in form of modules. Individual modules can also be expanded to higher bit configurations by cascading it with other modules of the same kind. IC industries use in-house designed modules for its products. These modules are not available due to proprietary and commercial reasons. This thesis presents a comprehensive insight into modular design approach and applies this approach towards implementing a microcontroller. A fully functional microprogrammable control unit is designed and simulated which could be later used as building block (module) for further designs.Item Optimal design of the fabrication parameters of integrated circuits.(Texas Tech University, 1975-08) Karmokolias, ConstantineNot availableItem Optimization techniques for cell assembly(Texas Tech University, 1988-12) Dutt, DebaprosadThis thesis concerns with the development of an automatic cell assembler. Given a floorplan containing leaf or composite cells and the interconnections between them, the assembler generates the optimized layout of the assembled cell. It automatically decides if the terminals on the adjoining cells must be connected either by pitch-matching or by inserting jogged wires. In the first case, the adjoining cells may need to be stretched along some vertical and/or horizontal stretch lines. The assembler computes the effect of stretching on the circuit elements and determines necessary stretch lines without any aid from the designer. In the later case, a 'jog' cell is introduced, dimensions of the cell and its position with respect to the neighboring cells in the floorplan are computed, and the interconnecting wires are routed in the 'jog' cell.Item Performance enhancement in column IV mobility, bandgap, and strain engineered MOSFETs(2003-12) Onsongo, David Masara, 1972-; Banerjee, SanjaySince the introduction of MOSFETs into the integrated circuit (IC), performance has been improved by device scaling. As device dimensions have scaled into the sub- 100nm regime, the challenges to device scaling have become increasingly significant and harder to surmount and other methods to complement scaling must be investigated and introduced into the industry. Enhancing carrier mobility can increase drive current. Compressively strained Si1-xGex and Si1-x-yGexCy provide a means of improving hole mobility, while tensile strained Si enhances both hole and electron mobility. The use of high-k gate dielectrics can increase MOSFET drive current while also increasing the ION to IOFF ratio. HfO2 has gained prominence in the search for a Si-compatible high-k dielectric. In this work, tensile strained Si1-yCy films and compressively strained, Si1-xGex and Si1-x-yGexCy films were grown via UHVCVD for device and process development studies. A nanometer-scale fabrication process was developed to fabricate sub-100nm PMOSFETs on these films, with both SiO2 and HfO2 being used as gate dielectrics. From these devices it was determined that Si1-xGex can be used in buried channel (with SiO2 gate dielectrics) and surface channel (with HfO2 gate dielectrics) to provide drive current enhancement in deeply scaled devices. This work demonstrates that higher mobility in Si1-xGex films can be used to recover the mobility degradation caused by using high-k gate dielectrics. In addition to drive current enhancement, it has been demonstrated that by process optimization, desirable short channel effects can be achieved in these devices. It is also shown that despite drive current enhancement at long channel length, deeply scaled Si1-x-yGexCy PMOSFETs do not provide drive current enhancement over Si. However, they have improved short channel effects. In recent times tensile strained Si has emerged as a favorable choice to improve carrier mobility and CMOS performance. As part of this work, hot-carrier degradation was studied in tensile-strained Si NMOSFETs. In addition to increased mobility and drive currents, it has been shown that these devices also possess decreased susceptibility to hot-carrier degradation. Simulation and experimental results indicate that this was due to the increased barrier to hot electron injection into the gate.Item Personal computer low-cost alternatives to automated test equipment(Texas Tech University, 2002-08) Yost, John C.A thesis exploring the use of PCs as an alternative test vehicle to expensive ATE and bench testing equipment. An example system is developed for comparing versatility, interface, and hardware capabilities. Results showed PC is most apphcable to testing SSI, MSI, and LSI circuit famihes. Future work is also explored for enhancing PC capabilities.