Test plan generation technique for complex integrated circuits

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dc.contributor.advisorAmbler, Tonyen
dc.creatorLee, Songjunen
dc.date.accessioned2011-06-09T21:47:57Zen
dc.date.accessioned2017-05-11T22:22:11Z
dc.date.available2011-06-09T21:47:57Zen
dc.date.available2017-05-11T22:22:11Z
dc.date.issued2002-12en
dc.descriptiontexten
dc.description.departmentElectrical and Computer Engineeringen
dc.format.mediumelectronicen
dc.identifier.urihttp://hdl.handle.net/2152/11614en
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.rights.restrictionRestricteden
dc.subjectIntegrated circuits--Testingen
dc.subjectIntegrated circuits--Design and construction--Cost effectivenessen
dc.titleTest plan generation technique for complex integrated circuitsen

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