Browsing by Subject "Software-defined radio"
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Item Circuit techniques for programmable broadband radio receivers(2013-12) Forbes, Travis Michael, 1986-; Gharpurey, RanjitThe functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF.Item Harmonic rejection mixers for wideband receivers(2013-05) Rafi, Aslamali Ahmed; Viswanathan, T. R., doctor of electrical engineering; Hassibi, ArjangThis dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming.Item Rapid reading for passive wireless coupled sensors(2012-08) Trivedi, Tanuj Kiranbhai; Neikirk, Dean P., 1957-; Wood, Sharon L.; Pasupathy, PraveenkumarThe objective of this thesis is to design and implement a rapid, reconfigurable and portable reader for wirelessly interrogating inductively coupled passive sensors. While the current method of impedance analyzer is sensitive and an accurate, the instruments used are bulky and slow, substantially hampering in-field testing and interrogation of sensors. Current methods cannot provide a quantifiable measure on minimum necessary read-speeds and instrument accuracy desirable for rapid sensing applications. This work summarizes the design and hardware implementation of two reader methods that address the aforementioned requirements. Both reader methods are based on a reflectometer approach: Swept-frequency Reflectometer Reader and Switched-frequency Interrogation Technique (SWIFT). The first method is a much faster alternative to in-lab and in-field testing for structural health monitoring, and is intended as an immediate replacement for the impedance analyzer method. Switched-frequency Interrogation is specifically designed to satisfy the need for rapid and accurate reading, potentially for in-motion sensing applications. This method provides a way of empirically relating minimum necessary read-time required for desired read-ranges. It also facilitates quantification of uncertainty in measurements, which is very critical in determining instrument accuracy in-field. The system design and implementation of both methods are described in detail and experimental results are presented to benchmark the performance of the readers. Issues of instrument reliability and practical limitations are also discussed, with potential solutions. Both methods are intended as universal techniques for wirelessly interrogating coupled passive sensors, not limited to their current form of implementation.Item Wireless transceiver for the TLL5000 platform : an exercise in system design(2009-12) Perkey, Jason Cecil; Gharpurey, Ranjit; McDermott, MarkThis paper will present the hardware system design, development, and plan for implementation of a wireless transceiver for The Learning Labs 5000 (TLL5000) educational platform. The project is a collaborative effort by Vanessa Canac, Atif Habib, and Jason Perkey to design and implement a complete wireless system including physical hardware, physical layer (PHY-layer) modulation and filters, error correction, drivers and user-interface software. While there are a number of features available on the TLL5000 for a wide variety of applications, there is currently no system in place for transmitting data wirelessly from one circuit board to another. The system proposed in this report is comprised of an external transceiver that communicates with a software application running on the TLL-SILC 6219 ARM9 processor that is interfaced with the TLL5000 baseboard. The details of a reference design, the hardware from the GNU Radio project, are discussed as a baseline and source of information. The state of the project and hardware design is presented as well as the specific portions of the project to which Jason Perkey made significant contributions.