Browsing by Subject "Semiconductor storage devices"
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Item Analysis and implementation of a generic pre-laser test(Texas Tech University, 2002) Kambalapalli, ManjulaThe growth of semiconductor industry is dependent on delivering good products. Semiconductor memory testing is very important to deliver good products to the costumers. Prelaser testing of memory is done to rectify the defects in the memory. This paper describes the various memory tests, compares them based on the fault coverage's offered by them and implements a generic program to test memory on a semiconductor wafer.Item Central processing unit built-in self-test and enhanced statistical defect analysis compression for static random access memory(Texas Tech University, 2003-08) Francis, David AThe percentage of digital signal processors (DSPs) occupied by embedded static random access memory (SRAM) has increased drastically over the years. As a result, static memory has become a prime contributor to the overall failure rate of DSP devices. Central Processing Unit Built hi Self Test (CPUbist) was thus developed in an effort to create a more economical and efficient method to test and repair such memories. CPUbist utilizes the power and speed of the on-chip processor, and demonstrates adequate and flexible memory fault coverage without the sacrifice of increased test time. This test method was used to not only test and create repair solutions for failing embedded SRAM, but also to map and compress bit fail data before offloading to the tester. To keep test cost at a minimum, the CPUbist programs were executed on the very low cost tester (VLCT), and data transfers were kept to a minimum by compressing fail data before offloading. All results obtained from CPUbist were then correlated with data from Membist, so as to ensure proper operation and to determine its level of effectiveness. The results of the correlation revealed that CPUbist can effectively test and repair DSP memories, in most instances at a faster rate than Membist.Item Electrical characterization of doped strontium titanate thin films for semiconductor memories(2002) Han, Jeong Hee; Lee, Jack Chung-YeungDoped strontium titanate (ST) thin films were investigated for highdensity memory applications. ST has become a promising candidate to replace conventional silicon oxide due to its high inherent dielectric constant, superior leakage characteristics, and good chemical stability. However, oxygen vacancies and the problems that arise as a result are one of the main drawbacks against this material. Resistance degradation is a serious reliability issue in perovskite titanate films and may be a result of oxygen vacancies. In this dissertation, an attempt to reduce the resistance degradation was made by doping the ST films with both niobium and lanthanum. Niobium is a Bsite donor in the perovskite, whereas lanthanum is an A-site donor. Both have an extra valence charge than the atom which it replaces in the crystal structure. With a higher valence charge, the number of oxygen vacancies is hoped to be reduced and result in better electrical performance. Experimental results showed that the degradation rate is reduced by doping with either niobium or lanthanum. A bilayer study was also performed to optimize the dielectric with the strengths of both doped and undoped strontium titanate and to distinguish the source of the oxygen vacancies. A study on the conduction mechanisms and dielectric dispersion was also performed. An additional study was made on the effect of iridium as a possible gate electrode for a MOS capacitor. Hafnium oxide was used as the high-permittivity oxide. The results observed showed that the capacitance was higher for iridium electrodes than those for platinum electrodes. However, both electrodes showed unacceptable frequency dispersion which may be caused by crude patterning techniques. A hysteresis review was also done for hafnium and zirconium oxides. It was observed that the hysteresis measured in the high-permittivity oxides are dependent on the accumulation sweep voltage due to the trapping and de-trapping of charge at the dielectric-silicon interface.Item Improved microprocessor memory testing algorithm(Texas Tech University, 2002-05) Cisneros, Carlos EnriqueThe task of designing, creating and implementing memory testing algorithms for semiconductor devices has become a more complex assignment over the last few years. This challenge has lead to a better understanding of the algorithms and all its surrounding elements. In this thesis we present improvements made on a memory testing algorithm, the so called "marchl3n" routine. A brief introduction to the SRAM type of memory is presented for a better understanding of the testing algorithm. Strong efforts were made in order to localize and correct the write pending problem. Using a proposed algorithm some modifications were performed to the "marchl3n" algorithm such that is unlikely to present this issue. Moreover, re-design of the "march 13n" algorithm was done to extend its particular use from production only to debug failures. In addition, code optimization was performed to the algorithm, in order to obtain better results from it.Item Non-volatile memory devices beyond process-scaled planar Flash technology(2007-12) Sarkar, Joy, 1977-; Banerjee, Sanjay; Gleixner, Robert J.Mainstream non-volatile memory technology dominated by the planar Flash transistor with continuous floating-gate has been historically improved in density and performance primarily by means of process scaling, but is currently faced with significant hindrances to its future scaling due to fundamental constraints of electrostatics and reliability. This dissertation is based on exploring two pathways for circumventing scaling limitations of the state-of-the-art Flash memory technology. The first part of the dissertation is based on demonstrating a vertical Flash memory transistor with nanocrystal floating-gate, while the second part is based on developing fundamental understanding of the operation of Phase Change Memory. A vertical Flash transistor can allow the theoretical minimum cell area and a nanocrystal floating-gate on the sidewalls is shown to allow a thinner gate-stack further conducive to scaling while still providing good reliability. Subsequently, the application of a technique of protein-mediated assembly of preformed nanocrystals to the sidewalls of the vertical Flash transistor is also demonstrated and characterized. This technique of ordering pre-formed nanocrystals is beneficial towards achieving reproducible nanocrystal size uniformity and ordering especially in a highly scaled vertical Flash cell, rendering it more amenable to scaling and manufacturability. In both forms, the vertical Flash memory cell is shown to have good electrical characteristics and reliability for the viability of this cell design and implementation. In the remaining part of this dissertation, studies are undertaken towards developing fundamental understanding of the operational characteristics of Phase Change Memory (PCM) technology that is expected to replace floating-gate Flash technology based on its potential for scaling. First, a phenomenon of improving figures of merit of the PCM cell with operational cycles is electrically characterized. Based on the electrical characterization and published material characterization data, a physical model of an evolving "active region" of the cell is proposed to explain the improvement of the cell parameters with operational cycles. Then, basic understanding is developed on early and erratic retention failure in a statistically significant number of cells in a large array and, electrical characterization and physical modeling is used to explain the mechanism behind the early retention failure.Item Novel flash memory with nanocrystal floating gate(2006) Liu, Yueran, 1975-; Banerjee, SanjayThe semiconductor market, despite some dips, has been generally increasing for a long time, and this increase is expected to continue in the coming decades. A large fraction of this market is from flash memory. The flash memory device has attracted more and more attention in recent years due to its advantages of high density, low power consumption and low cost. To achieve the further scaling down of the memory device, nanocrystals have been widely studied as the floating gate in the next generation of flash memory. This dissertation addresses the issue of gate stack scaling and voltage scaling for future generations of flash memory, and proposes solutions based on new memory structures and new materials that are compatible with current CMOS process flows. Our efforts to improve the performance of flash memories fall in three categories. First, a multi-layered tunnel barrier (VARIOT structure) is introduced, and the experimental VARiable Oxide results show that the programming speed of this device can be improved since the charges only need to penetrate a very thin barrier during the programming mode, while they face a much thicker barrier in the retention mode. Next, chaperonin GroEL protein molecules have been demonstrated to be a good candidate as the template to obtain a well ordered high density nanocrystal pattern. A flash memory device with SiC nanocrystals based on this technique is demonstrated. The retention time is enhanced due to the deep potential well created by SiC nanocrystals. Finally we demonstrate the improved chemical and electrical quality of Ge nanocrystals through passivation with a Si shell, whereby much better retention characteristics of flash memories with Ge nanocrystals having Si shell is obtained. We conclude with a study not to improve the device performance but to clarify a controversy about where exactly the trapped electrons are stored. The flash memory device with SiGe nanocrystals has been used to investigate the trapping site of the electrons in the floating gate. The experimental results show that the programmed electrons are stored in deep trap states of the surface of the semiconductor quantum dots, and those states are localized a few hundred meV below the semiconductor conduction band.Item Protein-mediated nanocrystal assembly for floating gate flash memory fabrication(2008-12) Tang, Shan, 1975-; Banerjee, SanjayAs semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work.Item A study on the nanocrystal floating-gate nonvolatile memory(2005) Lee, Jong Jin; Kwong, Dim-Lee