Browsing by Subject "Metal oxide semiconductor field-effect transistors"
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Item Bandgap engineering in vertical MOSFETs(2001-08) Chen, Xiangdong, 1972-; Banerjee, SanjayItem CMOS device and circuit technologies for on-chip smart temperature sensor(2012-05) Li, Yiran; Li, Changzhi; Gale, Richard O.This thesis work presents an all-CMOS on-chip smart temperature sensor for low voltage low power applications. Different temperature sensor front-end topologies have been designed and simulated in UMC 130nm process, AMI 0.5um process and IBM 90nm process respectively. The circuits designed in AMI 0.5um process and IBM 90nm process were fabricated and are being tested. The temperature sensor front-end in UMC 130nm process was designed to operate from 0°C to 120°C. The circuits designed in AMI 0.5um and IBM 90nm can be operated from -55°C to 125°C. Proportional-to-absolute-temperature (PTAT) voltage(s) and independent-of-absolute-temperature (IOAT) voltage with different sensitivities have been produced by different circuits. The temperature sensor front-end designed in UMC 130nm showed the capability to work as low as 0.6V. The one designed in AMI 0.5um operates from 1.2V. The one in IBM 90nm works from 0.5V [1]-[2]. Subthreshold MOSFETs, bulk-driven amplifier and Schottky Barrier Diodes (SBDs) have been adopted in different topologies for achieving low supply voltage and low power consumption. Dynamic element matching (DEM) and chopping have been used to improve the accuracy and robustness of the circuits. Different sizes of N-type Si SBDs were laid out and fabricated in AMI 0.5um process. The I-V relationships of these diodes have been characterized from -50°C to 120°C according to the test results. Model parameters such as ideality factor, effective barrier height and series resistance have been studied. The testing results showed the ability of SBDs to achieve the same current level and occupy a significantly smaller area compared with MOSFETs under the same process. The zero temperature coefficient (ZTC)-point-bias-voltage of SBDs are also lower than that voltage of MOSFETs. These characteristics imply great potential for using SBDs in low voltage low power circuit designs [3].Item A comprehensive study of 3D nano structures characteristics and novel devices(2008-12) Zaman, Rownak Jyoti; Banerjee, SanjaySilicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques.Item Development of a three-phase cryogenic synchronous rectifier(Texas Tech University, 1999-05) Haider, Mohammad RubelThis thesis details the design, fabrication and testing of prototypes of a three-phase Synchronous Rectifier, Power MOSFETs have been used as rectifying devices for synchronous rectification in combination with the necessary control circuits, Experiments have been performed in four different conditions, passive rectification using the body diodes of the MOSFETs at room temperature and at cryogenic temperature, synchronous rectification at room temperature and at cryogenic temperature. The results of these experiments show that synchronous rectification schemes significantly reduce the on-state voltage drop at room temperature and this reduction is more pronounced if the MOSFETs are cooled with liquid nitrogen. Reduction of the on-state voltage leads to the reduction in conduction losses and improves the power handling capability especially at cryogenic temperatures.Item Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: physics, reliability, and process development(2005) Rhee, Se Jong; Lee, Jack Chung-YeungItem Fast transient switching in bipolar junction transistors and metal-oxide-semiconductor field effect transistors(Texas Tech University, 1985-12) Menhart, SteveNot availableItem Gate voltage propagation delay in power MOSFETs(Texas Tech University, 1987-08) Mawanda-Kibuule, PaschalNot availableItem Hafnium dioxide gate dielectrics, metal gate electrodes, and phenomena occurring at their interfaces(2004) Schaeffer, James Kenyon; Ekerdt, John G.As metal-oxide-semiconductor field-effect transistor (MOSFET) gate lengths scale down below 45 nm, the gate oxide thickness approaches 1 nm equivalent oxide thickness. At this thickness, conventional silicon dioxide (SiO2) gate dielectrics suffer from excessive gate leakage. Higher permittivity dielectrics are required to counter the increase in gate leakage. Hafnium dioxide (HfO2) has emerged as a promising dielectric candidate. HfO2 films deposited using metal organic chemical vapor deposition are being studied to determine the impact of process and annealing conditions on the physical and electrical properties of the gate dielectric. This study indicates that deposition and annealing temperatures influence the microstructure, density, impurity concentration, chemical environment of the impurities, and band-gap of the HfO2 dielectric. Correlations of the electrical and physical properties of the films indicate that impurities in the form of segregated carbon clusters, and low HfO2 density are detrimental to the leakage properties of the gate dielectric. Additionally, as the HfO2 thickness scales, the additional series capacitance due to poly-silicon depletion plays a larger roll in reducing the total gate capacitance. To solve this problem, high performance bulk MOSFETs will require dual metal gate electrodes possessing work functions near the silicon band edges for optimized drive current. This investigation evaluates TiN, Ta-Si-N, Ti-Al-N, WN, TaN, TaSi, Ir and IrO2 electrodes as candidate electrodes on HfO2 dielectrics. The metal-dielectric compatibility was studied by annealing the gate stacks at different temperatures. The physical stability and effective work functions of metal electrodes on HfO2 are discussed. Finally, Fermi level pinning of the metal is a barrier to identifying materials with appropriate threshold voltages. The contributions to the Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the effective work function of platinum-HfO2-silicon capacitors. Oxygen anneals result in higher effective work functions for platinum on HfO2 than forming gas anneals. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the metal induced gap states model alone.Item Integrated circuit performance modeling using MOSFET in-line parameters(Texas Tech University, 2001-05) Thomas, Patricia DoloresCurrent methods of predicting the final-test performance of complex MOSFET devices are time consuming and can be unreliable. Also, large quantities of empirical data, required to develop a correlation to package-test speed, can only be collected weeks into the fabrication process. It would be useful early in the process to predict the final test IC performance before unnecessary commitments are made to a customer. To help solve this problem, statistical analysis of measurable, in-line parameters of a MOSFET transistor are used to develop process and circuit models of the devices. The parameters determined to have the greatest influence on speed performance, based on simulating IC speed, are determined. The known variation in these parameters can aid in better predictions of IC performance spreads.Item Investigation of electrical characteristics of III-V MOS devices with silicon interface passivation layer(2008-08) Zhu, Feng, 1978-; Lee, Jack Chung-YeungTo overcome the issues of mobility degradation and charge trapping in silicon high-κ MOSFET, a stacked Y₂O₃(top)/HfO2(bottom) gate dielectric on silicon substrate has been developed. Compared to the HfO₂ reference, the new dielectric shows similar scalability, but superior channel mobility and device reliability. The mobility improvement can be attributed to reduced remote phonon scattering, which is associated with the smaller ionic polarization of Y₂O₃, and the suppressed coulomb scattering due to less electron trapping in the bulk of high-κ layer, and reduced metal impurities in the substrate. The passivation mechanisms for the silicon IPL passivation technique in GaAs/[alpha]-Si IPL/high-κ MOS system have been investigated. We demonstrate the [alpha]-Si IPL thickness dependence and substrate type dependence of interface state density (Dit) for GaAs MOS capacitors. The interface state density is strongly correlated to the thickness and quality of un-oxidized Si IPL and its interaction with the underlying substrate. The results can be explained by the models related to the quantum well narrowing or the reduced local trap density as the unoxidized Si IPL layer thickness decreases. By using optimal Si IPL thickness (~10 Å), GaAs MOS devices can achieve the same interface quality, as its silicon counterpart. Using Si IPL to unpin the surface Fermi level, the selfaligned depletion-mode and enhancement-mode GaAs n-MOSFETs are demonstrated. In addition, the charge trapping and wear-out characteristics of the GaAs/Si IPL/HfO2/TaN MOS devices are systematically investigated. High performance In0.53Ga0.47As nMOSFETs with Si IPL and HfO2 gate oxide have been demonstrated. We systematically investigate the impacts of 1) Source/Drain activation temperature, 2) post deposition annealing (PDA) temperature, 3) In[subscrip 0.53]Ga[subscript 0.47]As channel doping concentration, 4) channel thickness and 5) Si IPL thickness on the transistor performances. With the [mu]m, V[subscript d]=50 mV), drive current of 158 mA/mm (L[subscript g]=5 [mu]m, V[subscript gs]=V[subscript th]+2 V, V[subscript d]=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. optimal combination of these impacting factors, excellent device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm, Vd=50 mV), drive current of 158 mA/mm (Lg=5 [mu]m, Vgs=Vth+2 V, Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided.Item The mechanism of the flatband voltage shift by capping a thin layer of Me₂O₃ (Me=Gd, Y and Dy) on SiO₂ and HfO₂-based dielectrics(2008-05) Zhang, Manhong, 1969-; Lee, Jack Chung-YeungContinuing to scale down the transistor size makes the introduction of high-k dielectric necessary. However, there are still a lot of problems with highk transistors such as worse reliability and Fermi-level pinning. In HfO₂, low crystallization temperature, fixed charge in the bulk and low quality of the Si/HfO₂ interface cause reliability problems. Fermi-level pinning results in high threshold voltage. For the first work in this dissertation, forming Hf1-xTaxO through doping HfO₂ with Ta is used to improve the crystallization temperature and electron mobility. Then, the fluorine passivation of high-k dielectrics is studied. With fluorine passivation, the electron mobility was improved in NMOSFETs with gate stacks of poly-Si/TaN/HfO₂/p-Si with thin TaN layers. Inserting a 1.5nm layer of HfSiON between TaN and HfO₂ completely blocked the fluorine atoms so that they could not reach the Si interface. Thus, no mobility was improved even with fluorine implantation. In order to decrease threshold voltage, we must study mechanisms of Fermi level pinning (FLP) in high-k gate stacks. We summarize three FLP mechanisms: (1) the dipole formation at the interface between metal gate and high-k dielectric due to hybridization; 2) the dipole formation through oxygen vacancy mechanism; (3) the dipole formation at the interface between high-k dielectric and interfacial SiO₂. The rest of dissertation focuses on the mechanism of Vfb shift by capping a thin layer of Me₂O₃ (Me=Gd, Y and Dy) on SiO₂ and HfO₂-based high-k dielectrics with TaN, W and Pt metal gate. It is proposed that the negative Vfb shift with TaN metal gate be due to the dipole formation at the interface between Me₂O₃ and the interfacial SiO₂. An XPS (X-ray photoelectron spectroscopy) study of Gd₂O₃ capping on SiO₂ indicates clear Si, O and Gd related bonding state change at the interface between Gd₂O₃ (or GdSiO) and the interfacial SiO₂. So the bonding state change is the root cause of the dipole formation. When there is an oxygen deficiency in Me₂O₃, another dipole formation through oxygen vacancy mechanism can also be observed. For a full understanding of the Vfb shift, all three FLP mechanisms must be considered.Item Metal-oxide-semiconductor devices based on epitaxial germanium layers grown selectively directly on silicon substrates by ultra-high-vacuum chemical vapor deposition(2009-05) Donnelly, Joseph Patrick, 1965-; Banerjee, SanjayThis document details experiments attempting to increase the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs) which are the mainstay of the semiconductor industry. Replacing the silicon channel with an ultra-thin epitaxial germanium layer grown selectively on a silicon (100) bulk wafer is examined in detail. The gate oxide chosen for the germanium devices is a high-k gate oxide, HfO2, and the gate electrode is a metal gate, tantalum-nitride. They demonstrate large improvements in drive current and mobility over identically processed silicon PMOSFETs. In addition to the planar germanium PMOSFETs, a process has been developed for 50nm and smaller germanium P-finFETs and N and P germanium tunnel-FETs. The patterning of sub-30nm wide and 230nm tall three dimensional fins has been done with electron beam lithography and dry plasma etching. The processes to deposit high-k gate oxide and metal gates on the sub-30nm wide fins have been developed. All that remains for the production of these devices is electron beam lithography with a maximum misalignment error of 40nm.Item Performance enhancement in column IV mobility, bandgap, and strain engineered MOSFETs(2003-12) Onsongo, David Masara, 1972-; Banerjee, SanjaySince the introduction of MOSFETs into the integrated circuit (IC), performance has been improved by device scaling. As device dimensions have scaled into the sub- 100nm regime, the challenges to device scaling have become increasingly significant and harder to surmount and other methods to complement scaling must be investigated and introduced into the industry. Enhancing carrier mobility can increase drive current. Compressively strained Si1-xGex and Si1-x-yGexCy provide a means of improving hole mobility, while tensile strained Si enhances both hole and electron mobility. The use of high-k gate dielectrics can increase MOSFET drive current while also increasing the ION to IOFF ratio. HfO2 has gained prominence in the search for a Si-compatible high-k dielectric. In this work, tensile strained Si1-yCy films and compressively strained, Si1-xGex and Si1-x-yGexCy films were grown via UHVCVD for device and process development studies. A nanometer-scale fabrication process was developed to fabricate sub-100nm PMOSFETs on these films, with both SiO2 and HfO2 being used as gate dielectrics. From these devices it was determined that Si1-xGex can be used in buried channel (with SiO2 gate dielectrics) and surface channel (with HfO2 gate dielectrics) to provide drive current enhancement in deeply scaled devices. This work demonstrates that higher mobility in Si1-xGex films can be used to recover the mobility degradation caused by using high-k gate dielectrics. In addition to drive current enhancement, it has been demonstrated that by process optimization, desirable short channel effects can be achieved in these devices. It is also shown that despite drive current enhancement at long channel length, deeply scaled Si1-x-yGexCy PMOSFETs do not provide drive current enhancement over Si. However, they have improved short channel effects. In recent times tensile strained Si has emerged as a favorable choice to improve carrier mobility and CMOS performance. As part of this work, hot-carrier degradation was studied in tensile-strained Si NMOSFETs. In addition to increased mobility and drive currents, it has been shown that these devices also possess decreased susceptibility to hot-carrier degradation. Simulation and experimental results indicate that this was due to the increased barrier to hot electron injection into the gate.Item Performance of power Mosferts at cryogenic temperatures(Texas Tech University, 1996-05) Mahmud, Zia UddinThe maximum power level that can be controlled by power MOSFETs is limited by the maximum allowable power dissipation. Recent publications^^ indicate, that operation of power MOSFETs at cryogenic temperatures will significantly (by more than an order of magnitude) reduce losses and increase their switching speed and power handling capability. The losses of power MOSFETs are conduction losses and switching losses due to either mechanism are reduced at cryogenic temperatures.Item Processing and reliability studies on hafnium oxide and hafnium silicate for the advanced gate dielectric application(2004) Choi, Rino; Lee, Jack Chung-YeungAs the CMOS integrated circuits reduce to the 100-nanometer regime and beyond, the conventional SiO2 based gate dielectric is facing serious challenges such as high leakage current, impurity diffusion, and dielectric thickness uniformity control across a 300 mm wafer. Consequently, high-k materials, which have higher dielectric constants (k) than SiO2, are expected to replace it as the gate insulator. Amongst all the materials investigated, HfO2 and its silicate appear to be the most promising candidates since they have thermodynamic stability in contact with silicon, reasonable energy bandgap (>5eV), moderate dielectric constant and good thermal expansion matching with Si. In this Ph.D. work, the issues with HfO2 and potential solutions to these problems are discussed. Since scaling of Hf-based high-k dielectrics has been limited due to the interfacial layer formation, NH3 surface nitridation has been investigated to reduce EOT and to improve reliability. Surface nitridation achieved a minimum EOT of 7.1Å, better thermal stability and higher breakdown field compared to a sample without surface nitridation. However, the surface nitridation exhibited adverse effects such as high hysteresis, lower interface quality and reduced carrier mobility. High-temperature forming gas (FG) prior to metallization successfully enhaced the carrier mobility of HfO2 gate dielectric MOSFETs with TaN gate electrode by improving HfO2/Si interface quality. Although improvement by high-temperature FG anneal was achieved, hydrogen atoms introduced by forming gas anneal can lead to unavoidable side effects such as poor NBTI and hot carrier degradation. Therefore, an attempt to reduce this degradation by using heavier deuterium atoms was executed. In addition to improved carrier mobility, improved reliability was also observed. Finally, the reliability issues of MOSFETs with hafnium silicate have been researched. A significant charge detrapping has been observed when the constant stress bias was removed. The rates of detrapping depend on the stress bias and time. Considering the fact that the real circuit operates at high frequency and low duty cycle, the reliability of high-k dielectric evaluated using conventional DC stress tests are excessively pessimistic to predict the long-term reliability of high-k gate dielectric. Polarity dependence of bias stress induced degradation was observed on the nMOSFET with HfSiON gate dielectric. Negative bias stress resulted in more significant increase of interface states and, accordingly, degradation of subthreshold swing than positive stress. It is suggested that the drain to gate stress on nMOSFET can damage the area of the high-k gate dielectric near the drain, resulting in asymmetric subthreshold swing degradation. Since this effect is more prominent in short channel MOSFETs, drain to gate stress during the off-state may play a greater role in the scaled devices.Item Scalable voltage reference for ultra deep submicron technologies(2005) Cave, Michael David; Davis, John H.A CMOS voltage reference architecture is shown that operates at a power supply that is equal to two threshold voltages. The circuit designed includes no more than two devices stacked between Vdd and Vss , thus allowing for the circuit to scale with device sizing (technology). The circuit is demonstrated in a 0.18µ and 0.09µ process that operates at a power supply voltage of 0.9V and 0.4V, respectfully. The dissertation discusses the motivation behind scaling the MOSFET transistor and the challenges that scaling introduces to analog circuit design in general. The voltage reference is a basic building block for most analog circuits, and therefore must be able to scale with technology. The temperature characteristics of silicon and MOSFET devices are discussed in order to develop analog circuits that demonstrate specific and controlled temperature characteristics. By describing the temperature characteristics of these devices with polynomials, the Method of Least Squares may be used to determine gain coefficients that give an optimum temperature independent voltage reference.Item Study of germanium MOSFETs with ultrathin high-k gate dielectrics(2004) Chen, Jer-hueih; Banerjee, Sanjay; Guha, SupratikThe continued scaling of Si CMOS devices has led to an increased attention to high-k gate dielectrics as replacements for SiO2, where eventually the physical thickness of SiO2 cannot be scaled further before gate oxide leakage becomes prohibitively large. However, a major challenge of replacing SiO2 with a high-k gate dielectric is that high-k Si MOSFETs exhibit degraded channel mobility. It is for this reason that Ge has recently received renewed attention as a possible replacement for Si in high-k CMOS devices, because its higher electron (2.5X) and hole (4X) bulk mobility relative to that of Si allows for the prospect of improved MOSFET channel mobility, while maintaining the potential to continue aggressive device scaling. Two high-k dielectric materials – Al2O3 and HfO2 – were studied . These films were deposited on bulk Ge using reactive atomic-beam deposition. Germanium MOS capacitors, p-MOSFETs and n-MOSFETs were fabricated and characterized. Ultrathin Al2O3 films with equivalent oxide thickness, teq, of 23Å were deposited on surface-nitrided Ge, with gate leakage currents 3 orders of magnitude lower than a SiO2 film of equivalent thickness, and hysteresis of less than 5mV. Significantly thinner films were achieved with HfO2, with the most aggressive HfO2/Ge gate stack having a teq ~ 11Å and gate leakage current that was 6 orders of magnitude less than that for a SiO2 film of equivalent thickness. Surface nitridation and post-deposition anneals were important in improving the quality of the high-k/Ge gate stacks. Surface nitridation reduced leakage current density, C-V hysteresis, charge trapping, interface state density, and inhibited interfacial layer formation which reduced the film’s equivalent oxide thickness. Germanium p-MOSFETs with ultrathin HfO2 films of varying thicknesses were characterized, with the thinnest HfO2 film having a teq of 10.5Å, and excellent gate leakage characteristics. For Ge p-MOSFETs with thicker HfO2 films (teq ~ 32Å), we observed a clear enhancement in hole mobility of about 1.4-1.6 times that a Si MOSFET (with HfO2 gate dielectric) control. However, hole mobility decreased with decreasing gate dielectric thickness, demonstrating that at ultrathin film thicknesses, additional mobility degradation mechanisms become significant. Germanium n-MOSFETs with ultrathin HfO2 films of varying thicknesses, ranging from teq ~ 16Å to 36Å, were studied. Extracted electron mobility of the Ge nMOSFETs were low, possibly due to high interface charge densities as well as high series resistances arising from incomplete source/drain phosphorus dopant activation.Item A study on electrical and material characteristics of hafnium oxide with silicon interface passivation on III-V substrate for future scaled CMOS technology(2008-05) Ok, Injo, 1974-; Lee, Jack Chung-YeungThe continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO₂ gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO₂ (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x10¹⁰ eV⁻¹cm⁻²), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO₂ film. HfO₂ based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility.Item A study on the material and device characteristics of hafnium oxynitride MOSFETs with TaN gate electrodes(2004) Kang, Changseok; Lee, Jack Chung-YeungHfO2 have been under intense investigation for gate dielectric application into the 70 nm technology nodes and beyond to replace conventional SiO2 or oxynitrides since it possesses a dielectric constant of 22 – 25, a large band gap of 5.6 eV with sufficient band offsets of larger than 1.5 eV, and is thermally stable in contact with silicon and metal gates. However, HfO2 is vulnerable to the diffusion of oxygen that causes formation of a low-k interfacial (silicon oxide or silicate) layer at the Si interface and boron penetration when combined with the p+ poly-Si gate technology. In addition, HfO2 crystallizes at relatively low temperature (<600 oC) unlike SiO2 that remains in amorphous phase through the semiconductor process involving high temperature annealing higher than 1000 oC. In this research, the focus was placed on the effects of nitrogen in HfO2 dielectrics to improve thermal stability (i.e. equivalent oxide thickness (EOT) increase by anneal and crystallization) of the dielectrics by surface treatment and nitrogen incorporation into the HfO2. In addition to the Hf-based dielectrics themselves, effects of Hf into conventional SiO2 dielectrics and the characteristics of TaN for gate electrode application were studied. The effects of Hf implanted into p-type Si substrates on the properties of n+ polycrystalline-Si/SiO2/Si capacitors and MOSFETs have been investigated. Flat-band voltages (Vfb ) and substrate doping concentrations ( NA ) calculated from high frequency C-V curves of the capacitors were not dependent on the doses of Hf. Also, electron channel mobility was not degraded by Hf contamination. The amount of Hf diffused into the Si substrate during the high- k dielectric imposed negligible effects on silicon based MOS device characteristics in terms of C-V, J-V characteristics and electron mobility. In this work, sputtered-TaN was mainly used as a gate electrode. Work functions of tantalum nitride (TaN) film before and after post-metal-annealing were ~ 4.15eV, and ~ 4.7 eV, respectively. A surface nitridation technique using NH3 anneal has been investigated to reduce interfacial reactions and consequently the equivalent oxide thickness (EOT) of TaN/HfO2/ Si MOS capacitors. For the same EOT, the nitrided samples showed 1 ~ 2 order of magnitude lower leakage current density compared to the non-nitrided ones. However, nitridation induced higher interface state density and larger hysteresis. The degraded interface quality due to the nitridation was improved by post-metal annealing (PMA). Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO2. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be similar to hafnium- silicon-oxynitride (HfSiON) while the IL of the HfO2 films seemed to be hafnium-silicate (HfSiO). HfON with nitrogen of ~ 5 atomic % at the interface resulted in an increase in crystallization temperature, higher dielectric constant, lower leakage current at the same equivalent oxide thickness (EOT) and high dielectric strength compared to HfO2. The improved electrical properties of HfON over HfO2 can be explained by the thicker physical thickness of HfON for the same EOT due to its higher dielectric constant as well as a more stable interface layer. High temperature forming gas anneal at 600oC for 30 min was effective in improving carrier mobility of nMOSFETs with HfON gate dielectrics. The effects of silicon and nitrogen profiles in gate dielectrics on the electrical and material properties of the Hf-based dielectric were investigated. To vary nitrogen profiles in the HfON films, 6-Å-thin Si layers were inserted in the different position of HfON films. By the insertion of Si layer, nitrogen profiles were modulated. The inserted Si leading to the nitrogen incorporation increased thermal stability. Highest mobility was observed at the dielectrics with Si layer inserted in the middle of HfON films.Item Systematic evaluation of metal gate electrode effective work function and its influence on device performance in CMOS devices(2006) Wen, Huang-Chun; Kwong, Dim-LeeAs the CMOS integrated circuits are reduced to the 100-nanometer regime, the conventional SiO2-based gate dielectrics are facing serious scaling challenges. High-k materials are expected to replace SiO2 as the gate insulator. However, metal gates are coherently needed to replace poly-Si due to the increase in threshold voltage for high-k stacks with poly-Si gates and the poly depletion effect. The challenge in metal gate research is to obtain metals with effective work function (EWF) values of ~5.0-5.2eV for p-MOS and 4.1-4.3eV for n-MOS. Although EWF should be determined predominately by the vacuum WF of the materials, it is observed that the EWF is different on high-k than on SiO2. One proposed mechanism to limit the EWF tuning on high-k dielectrics, and a possible inherent roadblock to the identification of band-edge metals, is the Fermilevel pinning effect Metal gate EWF has been systematically studied with the goal of identifying band-edge metal gate electrode candidates. The terraced oxide technique has been developed as the metric for accurate EWF extraction. A comparison of the literature Fermi-level pinning models with our experimental data shows that an intrinsic limitation (pinning at the high-k charge neutrality level) may not exist and the source of most EWF deviation on high-k is due to extrinsic contributions, such as interfacial reactions. Both the bulk metal characteristics and the interface properties between the metal and dielectric have been found to control overall EWF. Charges can be induced in the gate stack during device processing and shift the flatband voltage (Vfb). Engineering of the EWF by an interface dipole has been identified as a plausible approach for EWF tuning. Aluminum-containing electrode stacks and lanthanide electrode stacks are proposed as potential p-type and n-type metal candidates. The potential impact of candidate metal systems on device performance and reliability was studied, as well as other materials that may reveal implications for the influence of the electrode on the gate stack. Comparison of the deposition techniques, shows that even physical vapor deposited (PVD) metal electrodes can exhibit high performance. Metals with high O reactivity will reduce the high-k and consequently degrade electron mobility. No long term reliability concerns were observed for the candidate metals.