Browsing by Subject "Dielectrics"
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Item A study of the diffraction of microwaves by a dielectric straight edge(1966-08) Varnell, Gilbert LynnNot AvailableItem A study of the variation of the dielectric constant of air with pressure(Texas Tech University, 1934-08) Burkhalter, Allen HenryNot availableItem An investigation of pulsed high power microwave dielectric surface flashover(2012-05) Foster, Jonathan; Neuber, Andreas A.; Krompholz, Hermann G.; Hatfield, Lynn H.Breakdown events in high power microwave (HPM) systems have been a severely detrimental phenomenon and have inhibited the further development of HPM systems and technologies. The predictability of these events has proven difficult due to the presence of non-uniform microwave fields and the effects of specific gas species and pressures associated with various HPM applications. One particularly difficult aspect is the predictability of the appearance of initial electrons which initiate breakdown events. The source of these initial electrons is highly dependent upon the geometry and system in question. Once an electron appears in a breakdown region, the determination of the time to reach some critical electron density can also prove difficult due to the inherently statistical gaseous mechanisms involved with the avalanche event. It is the purpose of the investigation presented in this paper to provide some insight towards predicting the initiation of HPM breakdown events which could lead to better system reliability. The focus of this investigation assumes the presence of a dielectric interface to separate the radiating side from the microwave generation side of an HPM system. The research simulates a high altitude, low pressure environment for HPM propagation. In the event of breakdown at the dielectric interface, the transmitted microwaves could be rapidly cut off by way of reflection or absorption into the generated plasma. Various theoretical and experimental aspects regarding this phenomenon are discussed as well as the development of a statistical model which predicts HPM surface flashover events for various experimental conditions.Item Analyses of device characteristics in low voltage p-, new material n-, and dual-channel organic field-effect transistors(2008-05) Jeong, Yeon Taek, 1971-; Dodabalapur, Ananth, 1963-This dissertation consists of three main chapters: Pentacene-based low voltage pchannel organic filed-effect transistors (OFETs) with anodized gate dielectrics; Charge transport in N,N’-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) [PDI-8CN2] based n-channel OFETs; and Dual-channel OFETs. Pentacene-based low voltage pchannel OFETs were realized using three different anodized gate dielectrics: a 470 Å SiO2, a 1,700 Å Ta2O5, and an 800 Å Ta2O5 formed by anodizing an n-Si wafer, a sputtered Ta thin film, and an e-beam evaporated Ta layer, respectively. Devices with the anodized SiO2 gate dielectric exhibited decent characteristics at VDS ≤ -10 V and VG ≤ -4 V, and the device performance was further improved by an octyltrichlorosilane (OTS) treatment. The two anodized Ta2O5 gate dielectrics were successfully employed to fabricate devices with high mobility at VDS ≤ -5 V and VG ≤ -2.5 V for the 1,700 Å Ta2O5 devices, and at VDS ≤ -10 V and VG ≤ -5 V for the 800 Å Ta2O5 devices. A hexamethyldisilazane (HMDS) treatment and a mono-docecyl phosphate (MDP) treatment proved to remarkably enhance the characteristics of the two Ta2O5 devices. However, the two treatments had the opposite influence on the threshold voltages of the devices from each other because of the capacitance difference resulting from their molecular length difference. In order to establish the suitable charge transport mechanisms in PDI-8CN2 and related n-channel organic semiconductors, the gate voltage and temperature dependence of electrical behavior and the contact resistance effects were studied in PDI-8CN2 based OFETs. The dependence of electrical behavior such as mobility, field-dependent mobility, trap density, and off current on gate voltage and temperature was derived using the multiple trapping and release (MTR) model. The contact resistance effects were determined by calculating the contact-corrected linear regime mobility and contact resistance by means of a four-probe measurement technique. Organic dual-channel OFETs were realized using poly-3-hexylthiophene (P3HT), PDI- 8CN2, and a polymeric dielectric (Merck® DS121) as the p-channel, n-channel, and gate dielectric materials, respectively. Coupled with each other, the p-FET and the n-FET showed acceptable characteristics at │VDS│ ≤ 50 V and │VG│ ≤ 50 V. Both the p-FET mode and the n-FET mode responded to delivered IPA and ethanol vapors with reasonably high sensitivity, which suggests that these organic dual-channel devices are effectively applicable to organic chemical sensing.Item Characterization and reliability of HFO₂ and hfsion gate dielectrics with tin metal gate(2005) Krishnan, Siddarth A.; Lee, Jack Chung-YeungSince the invention of the integrated circuit in 1958, the semiconductor industry has progressed at a fiery pace, through aggressive shrinking of the transistor channel length and associated device dimensions. The problems associated with such aggressive scaling are many-fold and have been dealt with by clever modifications or additions to existing process technology. However, as the 65 nm technology node nears production, the semiconductor industry hits a fundamental physical limitation: The thickness of the gate dielectric, Silicon Dioxide (SiO2) has been reduced to such an extent that the tunneling leakage current through the gate stack is reaching untenable levels. High permittivity dielectrics or high-κ dielectrics are being investigated to replace SiO2 in order to preserve the capacitance while maintaining larger physical thickness to keep the leakage current down. However, the introduction of high-κ materials into the conventional process flow is rendered difficult by various issues. It has been shown that gate stacks with high-κ materials have severely degraded mobility, while possessing large densities of charge traps. Additional concerns include the pinning of Fermi level at the midgap of the silicon bandgap, yielding undesirable threshold voltages, dielectric phase separation in ternary high-κ materials, high interface state density, low crystallization temperature and growth of a low-κ interfacial layer. We present a systematic study of the reliability aspects of hafnium based dielectrics with TiN gate electrode, and propose a robust and reliabile dielectric for introduction into CMOS product flow. Stress induced leakage current or SILC is studied in thick HfO2 dielectrics with TiN gate electrode and it has been observed that significant low voltage SILC-like behavior is exhibited when nMOSFETs and pMOSFETs are stressed under positive biased stress. Such SILC behavior is also shown to be reversible when a negative voltage is applied after the stress, or if the devices are relaxed with a 0V bias. This reversible low-voltage SILC is attributed to electrons being trapped during the stress, which subsequently detrap during the I-V sweeps, leading to the appearance of SILC-like behavior. Mobility degradation in high-κ gate stacks is studied and it is proposed that the mobility degradation is a combination of remote coulomb scattering, due to fixed charges in the dielectric and phonon scattering. Thinning the high-κ dielectric down is offered as a solution to reduce the mobility degradation. Positive bias temperature instability is studied, and it is shown that the threshold voltage instability can be reduced to insignificant levels by reducing the thickness of the dielectric. However, the threshold voltage instability of thick high-κ dielectrics remains problematic and will need to be solved before high-κ gate stacks can be incorporated into low power applications. It is shown that incorporating nitrogen into the dielectric through plasma nitridation or thermal nitridation could be used to reduce charge trapping in thick dielectrics. Negative bias temperature instability is shown to be a combination of electron detrapping from the high-κ layer and interface state creation due to hole injection into the interfacial layer. Although the interface state creation is made slightly worse by thinning the dielectric down, the threshold voltage shift is still less significant in thin dielectrics. While the introduction of high-κ dielectrics can now be considered viable, caution needs to applied while integrating metal gates into the product flow, for the problem of fermi-level pinning still remains unsolved. An outline of all the remaining issues with such high-κ / metal gate gate stacks is presented at the end of this report.Item Charge injection threshold in Lexan and Acrylite(Texas Tech University, 1996-12) McCuistian, Brian TrentBulk breakdown in dielectrics occurs when the applied electric field exceeds a critical field and the insulating dielectric becomes conducting. This breakdown event damages the dielectric by producing a permanent channel of fractal dimension inside the dielectric. The resulting conducting structure is referred to as a tree because of its treelike structure. The production of electric field induced microvoids, or precursors, has been theorized to precede the breakdown event. Electric breakdown through solid dielectrics is heavily influenced by charge injected into the dielectric from electrodes. An experimental apparatus to study dielectrics stressed by impulse electric fields in a vacuum has been constructed. This apparatus is used to study several physical processes related to the initiation of electrical breakdown in polycarbonate (PC) and polymethylmethacrylate (PMMA) dielectrics. A critical field is found to exist below which no charge is injected into the dielectrics. This critical field for charge injection is slightly below the critical field for bulk breakdown. When an applied voltage produces fields greater than the critical field for charge injection, a space charge cloud is injected into the dielectric. Values of the critical field necessary for charge injection, total amount of injected charge, radius of the space charge cloud region and a limit on the time required to produce the space charge cloud region are obtained in this experiment. From these parameters, limits on the high field mobility of charge carriers, and trap densities in the materials are determined. After the electrical fields are applied to the dielectrics, the dielectrics are studied with an optical microscope to detect damage caused by charge injection. This damage may be experimental detection of precursors hypothesized by one theory of bulk breakdown. In addition, a computer simulation of dielectric breakdown, that introduces variables representing physical phenomena such as electron impact ionization, field ionization, and breakdown threshold, as well as the random structural nature of polymers and defects has been developed. These computer generated fractal breakdown structures are similar to experimentally produced breakdown trees.Item Charge trapping effects on mobility and threshold voltage instability in high-k gate stacks(2005) Sim, Jang Hoan; Kwong, Dim-LeeIn order to provide better performance and higher packing density on the limited space, scaling down of the channel length is essential in ULSI fabrication technologies. Although the thermally grown or rapid thermally grown oxynitride with EOT of 18~25Å has been introduced in the manufacturing area for the replacement of SiO2 to further scale technology, the technology for beyond 0.1Pm still needs further thickness scaling of SiO2 or oxynitride and is approaching the scaling limits. Therefore, new materials such as high-k dielectrics and metal gate electrodes have been investigated in order to ensure continued scaling of the technology. Among multiple candidates such as Ta2O5, TiO2, Al2O3, Y2O3, La2O3, ZrO2, the HfO2-based material has been presently considered the most attractive candidate for the gate dielectric application due to its high k value, better device performance and thermal stability, etc. However, various challenges for high-k devices implemetation include low mobility and threshold voltage instability, which can be affected by the quality of the interfacial oxide and charge trapping. In particular, transient charge trapping was proposed to be one of the main resources for mobility reduction. Even though several process modifications, such as nitridation and silicate formation, suggest the ways for improvement of high-k dielectrics device performance, the effect of these changes has not been yet studied systematically. The reliability issues of the hafnium-based dielectrics, such as TDDB, bias temperature instabilities, and hot carrier stability, needs to be addressed in order to introduce high-k technology in 45 nm technology node. In this work, charge trapping effects on channel carrier mobility with metal gate electrode are investigated. ALD (Atomic Layer Deposition) process can improve uniformity of high-k layer. Channel carrier mobility of the HfO2 dielectric is shown be to underestimated by the impact of fast transient electron trapping during D.C. measurements. By reducing transient charging, effective mobility, as well as performance in general, of the high-k transistors can be improved. Scaling the physical thickness of the HfO2 dielectric was demonstrated to result in less charge trapping and higher mobility. We have introduce a localized transient charging model, which indicates that a portion of the hot carrier stress (HCS) degradation is due to the cold channel carrier injection rather than hot carrier injection. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier trapping induces permanent damage of the dielectric while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.Item Compact gate capacitance and gate current modeling of ultra-thin (EOT ~ 1 nm and below) SiO₂ and high-k gate dielectrics(2006) Li, Fei, 1972-; Register, Leonard F.; Banerjee, SanjayThe Metal-Oxide-Silicon (MOS) gate dielectrics have to be scaled down to about 1 nm to 0.5 nm equivalent oxide thicknesses (EOTs) to maintain the projected gate control over the silicon channel for ultra-large-scale-integrated (ULSI) circuits in the next generation. Various high-dielectric-constant (high-κ) materials and metal gate electrodes are being studied heavily as the replacements for conventional SiO2 dielectrics and polysilicon gate electrode to overcome the increasingly deleterious gate leakage current and polysilicon related problems (polydepletion effects, B penetration, etc.) in conventional MOS devices. Furthermore, quantum mechanical (QM) effects and FermiDirac statistics in both the Si substrate (subband formation, wave function penetration effects, etc.) and gate dielectrics (direct and Fowler-Nordheim (F-N) tunneling effects) have to be fully understood and simulated to interpret the measured gate capacitance (CgVg) and gate current (Ig-Vg) behavior precisely. Although such behavior can be somewhat addressed in numerical studies of gate stacks, the increasing physical complexity of the problem has made it difficult to create compact models applicable to and below ~ 1 nm EOTs. And while such numerical Cg-Vg and Ig-Vg simulators can provide a physically accurate and comprehensive understanding of these effects, efficient analytic Cg-Vg and Ig-Vg models with similar accuracy are required for practical every-day device and ULSI circuit simulations. In this work, a computationally efficient and accurate physicallybased integrated gate capacitance and gate current model of MOS devices with advanced ultra-thin EOT oxides (down to ~0.5 nm) is introduced for current and future integrated circuit technology nodes. With the aid of self-consistent numerical Schrödinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E1 ∝ Fox 2/3), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration more accurately. The filling of excited states consistent with Fermi-Dirac statistics has been addressed. Within the same framework for surface potential and available carriers for tunneling, a modified version of the conventional Wentzel-Kramers-Brillouin (WKB) approximation allows for the effects of the abrupt material interfaces and non-parabolicities in complex bandstructures of the individual dielectrics on the tunneling current (both direct and F-N). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO2, Si3N4 and high- κ (e.g., HfO2) gate dielectrics on (100) Si with EOTs down to ~1 nm. The compact model has also been adapted to address interface states, and poly-depletion and polyaccumulation effects on gate capacitance. A nonlinear least-square fitting program is demonstrated for fast and automatic gate characterization and parameter extraction for the 45-nm CMOS technology node and beyond.Item Defect model for the electronic conduction and breakdown in dielectric thin films(Texas Tech University, 1987-12) Lin, Tsai-kuA stochastic model of defects has been developed to explain the electronic properties of dielectric thin film systems. Consequently, a reaction-diffusion (RD) type of equation is obtained. This model considers the dielectric thin film system as an open system, in which nonlinearities play important role for the instabilities of the system. The general experimental observations on the current-voltage characteristics are discussed. The microscopic picture of the conduction processes leading to breakdown is proposed. Several steps of conduction are predicted before the destructive breakdown of the film occurs. These conduction stages correspond to the microscopic states of the system and, consequently, closely related to the defects correlated states. Qualitatively, the microscopic states of the system are correlated with the growth stages of the film. The mechanisms of aging and annealing are also addressed under this reaction-diffusion equation. The following is the chapter by chapter summary.Item Deposition of epitaxial Si/Si-Ge/Ge and novel high-K gate dielectrics using remote plasma chemical vapor deposition(2003-08) Chen, Xiao, 1972-; Banerjee, Sanjay; Rabenberg, Llewellyn K.Both high quality epitaxial Si/Si-Ge/Ge films and novel high-k gate dieletrics have been deposited using an upgraded Remote Plasma Chemical Vapor Deposition (RPCVD) system. The upgrade of the RPCVD system consisted of two parts. The first part involved design and installation of a high-density inductively coupled plasma (ICP) source with its peripheral units, in place of an old surface analysis chamber. As a new deposition chamber, this chamber is capable of generating high plasma density with significantly lower ion energy. The second part involved modification of an existing deposition chamber for high-k film deposition. With the final integration of the new RPCVD system, better interfacial quality, lower thermal budget, less contamination and autodoping, and easier process control are expected. Experiments on epitaxial Si growth were conducted in the new RPCVD chamber in order to characterize growth dependence on different processing parameters. The process was extended to epitaxial Ge/SiGe films on Si that are beyond their Critical Layer Thickness (CLT). High quality epitaxial Si1-xGex (x>0.5) and Ge metastable films were achieved with epitaxial thicknesses at least 5 times higher than the corresponding CLT. High-k gate dielectric growth was performed in another modified deposition chamber. Low temperature RPCVD HfO2 was obtained with excellent physical and electrical characteristics. Finally, epitaxial Ge/SiGe and novel high-k dielectrics processes were integrated to fabricate MOS capacitors. These capacitors, with excellent structural and electrical properties, significantly increased the potential to fabricate high channel mobility MOSFET devices using RPCVD.Item Dielectric surface flashover in a simulated low earth orbit environment(Texas Tech University, 1995-05) Hegeler, FrankVirtually all concepts for the use of electrical energy at high voltages (for commercial, scientific or military applications) must utilize solid dielectrics as insulators. In general, surface flashover on insulators sets the limit on the applicable voltage of the system. For practical applications, scaling laws (i.e., empirical curves relating the flashover voltage to the gap distance) were formulated which describe the simplest cases in ideal geometrical configurations on the design of high voltage systems is usually based on unnecessarily high safety factors with severe limitations on high voltage amplitudes and power densities in a system. Understanding the mechanisms of surface flashover in the space environment is critical in increasing the dielectric flashover voltage by applying, for example, electric and magnetic shielding techniques. For this investigation, an experimental apparatus was designed and constructed as a coaxial system in order to operate electrical and optical sensors with high temporal resolution. Current, voltage, and soft x-ray emission are recorded by highly sensitive sensors which have a risetime on the order of one nanosecond. The plasma is generated by an electron cyclotron resonance plasma source and the ultra violet radiation originates from a UV enhanced Xenon arc lamp. This experiment is the first to investigate the early phase of dielectric breakdown in a simulated low earth orbit environment. The results show that the breakdown mechanisms are drastically altered with a plasma and UV environment, compared to the "pure" vacuum case. Dielectric breakdown with a plasma background shows a lower breakdown voltage and a different current amplification mechanism in the early phase of flashover, compared to measurements in vacuum without plasma. With UV illumination, the dielectric flashover voltage amplitude decreases and the pre-flashover current increases at a slower rate, compared to results without UV Low amplitude magnetic fields were applied and several magnetic insulation or shielding techniques were tested. Increases of the breakdown voltage amplitude of up to a factor of four were found with magnetic insulation for the UV case. With a plasma background, the duration of an applied voltage pulse can be increased by a factor of 2 without causing flashover compared to the case without external magnetic fields.Item The effects of post-ash cleaning and chemical treatments on the dielectric properties and reliability of Cu/low-k interconnect structures(2005) Borthakur, Swarnal; Ho, P. S.As IC devices continue to shrink, the interconnect delay dominates over the gate delay in the circuit. This has been the primary motivating factor for the industry’s move towards copper and low-κ interconnects. One of the obstacles in implementing a porous low-κ material in a dual damascene structure is the degradation in its dielectric properties due to etching and ashing processes. These processes deplete the carbon from the trench interfaces and increase the hydroxyl content in the dielectric. As a result, the dielectric constant increases and the leakage and reliability characteristics degrade. The electrical characteristics and reliability of a low-κ dielectric with different pore-size and distribution was studied. Due to the difference in pore size and distribution, the interfacial roughness is higher for the material with larger pore-size. This leads to higher defect density which causes higher leakage and degraded reliability characteristics. A low-κ material with smaller pore size and tighter distribution of pores will give better reliability characteristics. FTIR analysis of blanket MSQtype low-κ films shows that etching and ashing processes change the molecular structure by breaking the cage configuration of the Si-O molecules and forming more network Si-O bonds. The etching and ashing processes also increase the hydroxyl content of the dielectric and consequently make the surface more hydrophilic. The analysis shows that a chemical treatment with hexamethyldisilazane (HMDS) vapor restores the carbon content of the film to an extent and reduces the hydroxyl content. This repair of the damage and partial restoration of the κ value leads to better reliability characteristics. Post-ash thermo-chemical treatments were performed in Damascene Cu/low-κ structures. An HMDS vapor treatment, followed by an annealing, was found to recover the carbon content and reduce the hydroxyl content. Such a post-ash thermo-chemical treatment also improves the breakdown and reliability characteristics. HMDS followed by an anneal treatment successfully reduces the capacitance, and as a result the effective κ, by about 3%. This decrease will become more significant as κ values continue to be lowered. The trench side-wall interfacial defect density is reduced by a factor of about 5 and the reliability lifetime is improved by a factor of about 9. Post ash chemical treatments are a useful process step that can improve the reliability of the Cu/low-κ structure and also help in achieving the effective κ target.Item The effects of silicon, nitrogen and oxygen incorporation and oxygen-scavenging technique on performances of hafnium-based gate dielectric MOSFETs(2006) Choi, Changhwan; Lee, Jack Chung-YeungThe continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV-1 cm -2), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. According to ITRS (International Technology Roadmap for Semiconductor) roadmap, the EOT (equivalent oxide thickness) in MOSFETs for next generation technology node must be below ~15Å for both high performance logic application like microprocessor and low power application such as mobile electronics. However, as the dramatic scaling-down is continuously needed, ultra thin silicon dioxide cannot be useful any more as a gate dielectric because the use of ultra thin SiO2 gate dielectrics gives rise to a number of problems, including high gate leakage current, reduced drive current, reliability degradation, B (boron) penetration, and the need to grow ultra thin and uniform layer. Especially, the physical limit and reliability problem of ulta thin SiO2 result from significantly increased direct tunneling current in such a thin region. Therefore, the need for new gate dielectric materials is emerging to reduce leakage current while maintaining a low EOT. Many materials with a dielectric constant higher than that of SiO2, known as high k dielectrics, have been being investigated in order to identify a SiO2 replacement. So far, HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The phase transformation due to crystallization of dielectric can provide the formation of gain boundary that will act as high oxygen or dopants diffusivity path, making EOT scaling problematic and causing device failure with high leakage current. Nitrogen incorporation into high k materials has been investigated to achieve further scaling and improve thermal and electrical stability because nitrogen is known to suppress oxygen diffusion, and reduce low k interfacial layer growth at the Si interface. However, nitrogen incorporation alone can result in several potential problems. Since nitrogen is likely to bind to Si, most of the nitrogen incorporated tends to pile up at the Si interface. This leads to an increased interface trapped charge density, increased hysteresis and lower channel mobility due to coulombic scattering. Also, the amount of nitrogen incorporated can be limited due to nitrogen out-diffusion during anneals. A potential solution to these problems is incorporating Si to modulate the nitrogen profile since Si traps nitrogen and suppresses nitrogen out-diffusion. In the first part of this study, the effects of nitrogen and silicon on Hf-based MOSFET performances and BTI (Bias Temperature Instability) characteristics have been investigated. Nitrogen profile has been modulated by inserting Si layer into HfOxNy. Nitrogen incorporation enhanced Vth shift for both PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). However, BTI degradation is significantly suppressed by the Si insertion. This improvement can be attributed to the reduction of oxide bulk trapped as well as interface trapped charge generation resulting from the insertion of Si layer. Although nitrogen incorporation reduces interfacial reaction and results in aggressive thinning such as EOT below10Å, which is required for beyond 65nm design rule, it also induces disadvantages such as higher hysteresis, higher charge trapping and degraded channel carrier mobility due to trap charges caused by nitrogen itself. Therefore, for aggressive scaling with good interface quality, novel process without using nitrogen, which can suppress low k interfacial regrowth, should be delivered. Some transition metals like Hf, Zr and Ti have very high oxygen solubility as well as negative free energy of oxide formation. These properties can be used to decompose SiO2 like low k interfacial oxide upon appropriate annealing (i.e., oxygen scavenging effect) and produce further EOT scaling. As for second part of this study, for highly scaled gate dielectric application, a novel oxygen scavenging approach has been proposed and investigated. A novel process has been developed to achieve ultra-thin gate dielectrics (EOT<0.7nm) without involving nitrogen incorporation by engineering interface oxide thickness. Interfacial oxide formation was suppressed by the “oxygen-scavenging effect” using Hf metal on underlying HfO2 device structure with appropriate annealing. The scavenging Hf metal layer consumes oxygen sources leading to further scaling still using undoped HfO2. Using this fabrication approach, EOT of ~0.9nm after conventional self-aligned MOSFET process was successfully obtained. In addition, further EOT improvement (EOT: 0.55~0.60nm) was realized in conjunction with nitrogen incorporation using scavenging effect. Excellent charge trapping and MOSFET characteristics have been demonstrated.Item Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: physics, reliability, and process development(2005) Rhee, Se Jong; Lee, Jack Chung-YeungItem Gate dielectrics on strained SiGe(2002-12) Ngai, Tat; Banerjee, SanjayBuried channel SiGe PMOSFET performance is degraded by the requirement of Si caps. However, fabrication of surface channel SiGe PMOSFETs has rarely been successful due to gate oxide problems. Low temperature deposited SiO2 using remote plasma CVD (RPCVD) and high-k gate dielectric ZrO2 using DC magnetron reactive sputtering have been investigated for SiGe applications in this work. A low temperature gate quality silicon dioxide process has been developed using Remote Plasma Chemical Vapor Deposition (RPCVD). By carefully controlling the background water concentration, a high quality SiO2/Si interface can be achieved even without the pre-oxidation. RPCVD oxide films deposited on Si have excellent as-deposited interfacial (Dit ~ 1x1010 cm -2eV-1) and bulk (Ebd > 10 MV/ cm) electrical properties. However, SiGe MOSFETs with high quality RPCVD SiO2 still under-perform Si devices because of a poor interface. Low temperature water vapor annealing seems to be very effective to passivate the dangling bonds at the SiO2/SiGe interface. More than 20% transconductance improvement is observed in SiGe devices after water vapor annealing. This dissertation also reports the electrical properties of a high-k material, ZrO2, deposited directly on SiGe, without the use of a Si cap layer or a passivation barrier. ZrO2 thin films of equivalent oxide thickness (EOT) down to 16.5 Å were deposited on strained SiGe layers by reactive sputtering. Results indicate that ZrO2 films on SiGe have good interfacial properties and low leakage currents. Silicon and surface channel SiGe PMOSFETs using a ZrO2 gate dielectric with EOT less than 20 Å was fabricated. Mobility enhancement is also observed in SiGe devices. ZrO2 shows great promise as an alternative gate dielectric for SiGe applications.Item Germanium MOS devices integrating high-k dielectric and metal gate(2007-05) Bai, Weiping, 1972-; Kwong, Dim-LeeThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Item Germanium MOS devices integrating high-k dielectric and metal gate(2007) Bai, Weiping; Kwong, Dim-LeeItem Hafnium dioxide gate dielectrics, metal gate electrodes, and phenomena occurring at their interfaces(2004) Schaeffer, James Kenyon; Ekerdt, John G.As metal-oxide-semiconductor field-effect transistor (MOSFET) gate lengths scale down below 45 nm, the gate oxide thickness approaches 1 nm equivalent oxide thickness. At this thickness, conventional silicon dioxide (SiO2) gate dielectrics suffer from excessive gate leakage. Higher permittivity dielectrics are required to counter the increase in gate leakage. Hafnium dioxide (HfO2) has emerged as a promising dielectric candidate. HfO2 films deposited using metal organic chemical vapor deposition are being studied to determine the impact of process and annealing conditions on the physical and electrical properties of the gate dielectric. This study indicates that deposition and annealing temperatures influence the microstructure, density, impurity concentration, chemical environment of the impurities, and band-gap of the HfO2 dielectric. Correlations of the electrical and physical properties of the films indicate that impurities in the form of segregated carbon clusters, and low HfO2 density are detrimental to the leakage properties of the gate dielectric. Additionally, as the HfO2 thickness scales, the additional series capacitance due to poly-silicon depletion plays a larger roll in reducing the total gate capacitance. To solve this problem, high performance bulk MOSFETs will require dual metal gate electrodes possessing work functions near the silicon band edges for optimized drive current. This investigation evaluates TiN, Ta-Si-N, Ti-Al-N, WN, TaN, TaSi, Ir and IrO2 electrodes as candidate electrodes on HfO2 dielectrics. The metal-dielectric compatibility was studied by annealing the gate stacks at different temperatures. The physical stability and effective work functions of metal electrodes on HfO2 are discussed. Finally, Fermi level pinning of the metal is a barrier to identifying materials with appropriate threshold voltages. The contributions to the Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the effective work function of platinum-HfO2-silicon capacitors. Oxygen anneals result in higher effective work functions for platinum on HfO2 than forming gas anneals. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the metal induced gap states model alone.Item High-permittivity dielectrics and high mobility semiconductors for future scaled technology: Hf-based High-K gate dielectrics and interface engineering for HfO₂/Ge CMOS device(2006) Lu, Nan; Kwong, Dim-LeeFor more than 40 years, MOS device technologies have been improving at a dramatic rate. These technologies need to meet the requirements of performance (speed), low static (off-state) power, and a wide range of power supply and output voltage to fuel market expansion. The greater performance at lower cost requires an increased circuit density and shrunken dimensions. The rapid shrinking of the transistor feature size has forced gate dielectric thickness decrease, which pushes SiO2 down to the physical limit. Currently, high permittivity material, such as HfO2, has been extensively studied due to its suitable dielectric constant (22-25), wide band gap (~5.6eV) and thermal stability in contact to Si. However, high k dielectrics have also faced lots of integration challenges, such as charge trapping and mobility degradation. Moreover, as the EOT of HfO2 gate dielectric is scaled down to the sub-nm regime, the gate leakage current increases quickly and is not acceptable for any practical application. In this research, the Hf-based higher k HfTaTiO and HfTiAlO gate dielectrics are demonstrated with both dielectric constants more than 25. The stability and scalability are investigated. Both dielectrics can be scaled down to below 1nm with acceptable leakage current. Improved mobility and reliability are studied. In addition, further power-performance gain is likely to be achieved by incorporating the benefit of the ultra-high channel mobility offered by Ge semiconductor. Changing the substrate from silicon to germanium brings new challenges in the formation of high k gate stacks. The poor quality of Ge native dielectric for gate insulator and field isolation has been one of the problems. The novel pre-gate clean has been developed for effective native oxide removal. Two interface passivation processes, NH3 annealing and Si interlayer, have been demonstrated. They reduce the leakage current density, C-V hysteresis and interface state density. Ge diffusion model is proposed and it suggests the necessity of a proper surface preparation prior to the dielectric film deposition. All the new materials and process development in this research present some potential solutions to enable high performance and low power CMOS for future technology.Item III-V channel MOS devices with atomic-layer-deposited high-k gate dielectrics : interface and carrier transport studies(2008-12) Shahrjerdi, Davood, 1980-; Banerjee, SanjayThe performance scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over four decades. Addressing the current challenges with CMOS scaling, the 2005 edition of International Technology Roadmap for Semiconductors has predicted the need for so-called technology boosters involving new materials for the gate dielectric and the channel as well as innovative structures. Theoretical studies suggest that the incorporation of high-mobility channel materials such as germanium and III-Vs could outperform bulk Si technology in terms of switching characteristics. Hence, this has recently led to tremendous research activity to explore the prospects of III-V materials for CMOS applications. Nevertheless, technological challenges such as formation of highquality interface between gate dielectric and III-V channel have hindered the demonstration of enhancement-mode III-V MOSFETs. Hence, tremendous effort has been devoted to study the exact origin of Fermi level pinning at the oxide/III-V interface. On the other hand, the advent of high-k materials has opened up the possibility of exploring new channel materials, for which it is challenging to achieve high-quality interface analogous to that of SiO2 on Si. Lately, III-Vs have been extensively explored in order to find compatible gate dielectrics which can unpin the Fermi level at the interface. Amongst various schemes, atomic layer deposition of high-k dielectrics offers some unique advantages such as reduction of GaAs interfacial oxides upon high-k deposition through an appropriate choice of precursor chemistry. The chief focus of this dissertation is to develop a simple wet clean process prior to high-k deposition, suitable for III-V substrates. The impact of various chemical treatments of GaAs substrates on the properties of high-k/GaAs interface was studied through extensive material and electrical characterization methods. The suitability of the ALD-grown high-k gate dielectrics on GaAs for MOSFET fabrication was explored. Charge trapping was found to result in significant errors in mobility extraction in high-k GaAs interface, where the role of high-k is not well understood. Hence, pulsed I-V and QV measurements and galvanomagnetic effects were utilized in order to directly measure the inversion charge in the channel without being affected by the charge traps as much as possible. It was also found that the material studies on GaAs substrates can be readily extended to other III-V channels, such as InGaAs.
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