Compact gate capacitance and gate current modeling of ultra-thin (EOT ~ 1 nm and below) SiO₂ and high-k gate dielectrics



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The Metal-Oxide-Silicon (MOS) gate dielectrics have to be scaled down to about 1 nm to 0.5 nm equivalent oxide thicknesses (EOTs) to maintain the projected gate control over the silicon channel for ultra-large-scale-integrated (ULSI) circuits in the next generation. Various high-dielectric-constant (high-κ) materials and metal gate electrodes are being studied heavily as the replacements for conventional SiO2 dielectrics and polysilicon gate electrode to overcome the increasingly deleterious gate leakage current and polysilicon related problems (polydepletion effects, B penetration, etc.) in conventional MOS devices. Furthermore, quantum mechanical (QM) effects and FermiDirac statistics in both the Si substrate (subband formation, wave function penetration effects, etc.) and gate dielectrics (direct and Fowler-Nordheim (F-N) tunneling effects) have to be fully understood and simulated to interpret the measured gate capacitance (CgVg) and gate current (Ig-Vg) behavior precisely. Although such behavior can be somewhat addressed in numerical studies of gate stacks, the increasing physical complexity of the problem has made it difficult to create compact models applicable to and below ~ 1 nm EOTs. And while such numerical Cg-Vg and Ig-Vg simulators can provide a physically accurate and comprehensive understanding of these effects, efficient analytic Cg-Vg and Ig-Vg models with similar accuracy are required for practical every-day device and ULSI circuit simulations. In this work, a computationally efficient and accurate physicallybased integrated gate capacitance and gate current model of MOS devices with advanced ultra-thin EOT oxides (down to ~0.5 nm) is introduced for current and future integrated circuit technology nodes. With the aid of self-consistent numerical Schrödinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E1 ∝ Fox 2/3), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration more accurately. The filling of excited states consistent with Fermi-Dirac statistics has been addressed. Within the same framework for surface potential and available carriers for tunneling, a modified version of the conventional Wentzel-Kramers-Brillouin (WKB) approximation allows for the effects of the abrupt material interfaces and non-parabolicities in complex bandstructures of the individual dielectrics on the tunneling current (both direct and F-N). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO2, Si3N4 and high- κ (e.g., HfO2) gate dielectrics on (100) Si with EOTs down to ~1 nm. The compact model has also been adapted to address interface states, and poly-depletion and polyaccumulation effects on gate capacitance. A nonlinear least-square fitting program is demonstrated for fast and automatic gate characterization and parameter extraction for the 45-nm CMOS technology node and beyond.