Browsing by Subject "Analog-to-digital converters--Calibration"
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Item A background calibration technique and self testing method for the pipeline analog to digital converter(2004) Yoo, Jae Ki; Swartzlander, Earl E.Analog to digital converters (ADCs) are the fundamental building blocks in highly integrated mixed-signal integrated circuits. Among several ADC architectures, the pipeline ADC is suitable for high sampling rate and high resolution, so it is widely used in many integrated applications such as, wireless transceivers, camcorders, portable video devices. In this dissertation, a new digital background calibration technique with two redundant stages is proposed. Due to the redundant stages, calibration cycles can be scheduled to the pipeline stages during normal operation. The basic building blocks are the same as the building blocks in a normal pipeline ADC and no extra design time is required for dedicated calibration ADCs or DACs. The technique can calibrate all the gain errors, offset errors and the non-linearity errors of the ADC except for the front-end S/H. When compared to the normal digital calibrated pipeline ADC, the digital hardware complexity is slightly increased. When compared to other background calibration techniques, it represents a compromise solution between with and without additional calibration converters. It is also suitable for converting high frequency input signals since there is nothing inherent causes in the algorithm that will degrade the performance for high input frequencies. A self-generated random signal based on the congruential mapping found in pipeline A/D converters is used as the test signal stimulus for histogram test. Almost no extra analog components are required for this random signal generation. The testing technique can be extended to in-field background verification if the converter is calibrated using skip-and-fill background calibration method.Item Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter(2003) Gan, Jianhua; Abraham, Jacob A.; Yan, ShouliIt is very challenging to build precise analog circuits in deep sub-micron and nanometer VLSI fabrication technology. Advanced calibration methods are crucial in designing high performance analog and mixed-signal VLSI circuits. We present a non-binary capacitor array calibration method for a high performance successive approximation analog-to-digital converter (ADC). We show that the capacitor weights are successively refinable under the Markov condition using the rate-distortion theory. Using the analogy to discrete memoryless channel with interference known to the encoder, we show that the interference will not limit the final calibration accuracy if the calibration algorithm adapts to the interference. The capacitor array calibration algorithm is based on a perceptron learning rule, originally developed for Artificial Intelligence applications. It takes advantage of the redundancy in the non-binary capacitor array and the noise in the system to generate the learning cases. We propose a mixed-signal micro-controller architecture to efficiently implement the capacitor array calibration algorithm. A non-binary capacitor array with 20 capacitors is used to design a 16-bit successive approximation ADC. We discuss the design and trade-off of each circuit block in the ADC. We model the thermal noise, flicker noise, power supply interference, charge leakage and harmonic distortion in MATLAB. The calibration is robust under the influence of these nonidealities. The capacitor weights are adaptively calibrated to match the physical capacitors with up to 22-bit accuracy. Capacitor matching is not a limiting factor to the accuracy. The calibration time is about 50 ms. The calibration algorithm can also be used in other mixed-signal circuits to relax the requirement on analog circuits.