A background calibration technique and self testing method for the pipeline analog to digital converter



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Analog to digital converters (ADCs) are the fundamental building blocks in highly integrated mixed-signal integrated circuits. Among several ADC architectures, the pipeline ADC is suitable for high sampling rate and high resolution, so it is widely used in many integrated applications such as, wireless transceivers, camcorders, portable video devices. In this dissertation, a new digital background calibration technique with two redundant stages is proposed. Due to the redundant stages, calibration cycles can be scheduled to the pipeline stages during normal operation. The basic building blocks are the same as the building blocks in a normal pipeline ADC and no extra design time is required for dedicated calibration ADCs or DACs. The technique can calibrate all the gain errors, offset errors and the non-linearity errors of the ADC except for the front-end S/H. When compared to the normal digital calibrated pipeline ADC, the digital hardware complexity is slightly increased. When compared to other background calibration techniques, it represents a compromise solution between with and without additional calibration converters. It is also suitable for converting high frequency input signals since there is nothing inherent causes in the algorithm that will degrade the performance for high input frequencies. A self-generated random signal based on the congruential mapping found in pipeline A/D converters is used as the test signal stimulus for histogram test. Almost no extra analog components are required for this random signal generation. The testing technique can be extended to in-field background verification if the converter is calibrated using skip-and-fill background calibration method.