A data interface for ultra high speed ADC integrated circuits
| dc.contributor.advisor | Aziz, Adnan | |
| dc.creator | Castro Scorsi, Rafael | en |
| dc.date.accessioned | 2013-12-18T21:56:22Z | en |
| dc.date.accessioned | 2017-05-11T22:40:43Z | |
| dc.date.available | 2017-05-11T22:40:43Z | |
| dc.date.issued | 2011-12 | en |
| dc.date.submitted | December 2011 | en |
| dc.date.updated | 2013-12-18T21:56:23Z | en |
| dc.description | text | en |
| dc.description.abstract | Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in order to keep up with the faster data rates while providing very high data integrity. The objective of this project was to design an inter-IC ADC interface for converters with data bandwidths as high as 56 Gigabytes per second. The main goal for this project was to create a mechanism for interfacing a general-purpose high-speed ADC integrated circuit with an FPGA. This will enable applications that can benefit from the reprogrammability offered by FPGAs as well as those that could not justify a monolithic integrated solution for cost reasons. The interface presented is based on the physical layer of the IEEE 10GBASE-KR specification for 10 Gigabit Ethernet (10GE). Leveraging this specification provides significant benefits as it defines most of the services required by the interface, such as effcient encoding and forward error correction. Furthermore, using an interface as widely used as 10GBASE-KR leverages significant validation work as well as widespread support in mainstream FPGAs and by IP providers. The report will provide an analysis of the requirements of the ADC interface and a description of the architecture proposed. One key aspect of the design of the system was the analysis of the e ects of random bit errors in the channel and how to deal with them while making a robust interface. The causes of error are described and the critical sections of the system were simulated to validate the choice of Forward Error Correction solution. Finally, the report describes the working prototype system built in an FPGA board and provides a description of the performance achieved. | en |
| dc.embargo.lift | 12/1/2012 | en |
| dc.embargo.terms | 12/1/2012 | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/2152/22769 | en |
| dc.language.iso | en_US | en |
| dc.subject | High speed ADC | en |
| dc.subject | 10 gigabit ethernet | en |
| dc.subject | ADC interface | en |
| dc.title | A data interface for ultra high speed ADC integrated circuits | en |