Architectural Support for Efficient Communication in Future Microprocessors
| dc.contributor | Kim, Eun Jung | |
| dc.creator | Jin, Yu Ho | |
| dc.date.accessioned | 2010-01-16T00:10:47Z | |
| dc.date.accessioned | 2017-04-07T19:54:30Z | |
| dc.date.available | 2010-01-16T00:10:47Z | |
| dc.date.available | 2017-04-07T19:54:30Z | |
| dc.date.created | 2009-05 | |
| dc.date.issued | 2010-01-16 | |
| dc.description.abstract | Traditionally, the microprocessor design has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip continues to increase, the design of communication architecture has become a crucial and dominating factor in defining performance models of the overall system. On-chip networks, also known as Networks-on-Chip (NoC), emerged recently as a promising architecture to coordinate chip-wide communication. Although there are numerous interconnection network studies in an inter-chip environment, an intra-chip network design poses a number of substantial challenges to this well-established interconnection network field. This research investigates designs and applications of on-chip interconnection network in next-generation microprocessors for optimizing performance, power consumption, and area cost. First, we present domain-specific NoC designs targeted to large-scale and wire-delay dominated L2 cache systems. The domain-specifically designed interconnect shows 38% performance improvement and uses only 12% of the mesh-based interconnect. Then, we present a methodology of communication characterization in parallel programs and application of characterization results to long-channel reconfiguration. Reconfigured long channels suited to communication patterns enhance the latency of the mesh network by 16% and 14% in 16-core and 64-core systems, respectively. Finally, we discuss an adaptive data compression technique that builds a network-wide frequent value pattern map and reduces the packet size. In two examined multi-core systems, cache traffic has 69% compressibility and shows high value sharing among flows. Compression-enabled NoC improves the latency by up to 63% and saves energy consumption by up to 12%. | |
| dc.identifier.uri | http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-746 | |
| dc.language.iso | en_US | |
| dc.subject | computer architecture, on-chip interconnection network, performance evaluation | |
| dc.title | Architectural Support for Efficient Communication in Future Microprocessors | |
| dc.type | Book | |
| dc.type | Thesis |