Investigation of 10-bit SAR ADC using flip-flip bypass circuit
dc.contributor.advisor | Sun, Nan | |
dc.creator | Fontaine, Robert Alexander | en |
dc.date.accessioned | 2014-04-15T20:02:13Z | en |
dc.date.accessioned | 2017-05-11T22:55:40Z | |
dc.date.available | 2017-05-11T22:55:40Z | |
dc.date.issued | 2013-12 | en |
dc.date.submitted | December 2013 | en |
dc.date.updated | 2014-04-15T20:02:13Z | en |
dc.description | text | en |
dc.description.abstract | The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed. | en |
dc.description.department | Electrical and Computer Engineering | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.uri | http://hdl.handle.net/2152/24011 | en |
dc.subject | SAR | en |
dc.subject | Successive Approximation Register | en |
dc.subject | ADC | en |
dc.subject | Flip-flop bypass | en |
dc.title | Investigation of 10-bit SAR ADC using flip-flip bypass circuit | en |
dc.type | Thesis | en |