Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack

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dc.contributor.advisorBanerjee, Sanjayen
dc.contributor.advisorRegister, Leonard F.en
dc.creatorFan, Yang-yuen
dc.date.accessioned2008-08-28T21:26:45Zen
dc.date.accessioned2017-05-11T22:15:45Z
dc.date.available2008-08-28T21:26:45Zen
dc.date.available2017-05-11T22:15:45Z
dc.date.issued2002en
dc.descriptiontexten
dc.description.departmentElectrical and Computer Engineeringen
dc.format.mediumelectronicen
dc.identifierb56748681en
dc.identifier.oclc56043363en
dc.identifier.proqst3110604en
dc.identifier.urihttp://hdl.handle.net/2152/567en
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subject.lcshGate array circuitsen
dc.subject.lcshDielectricsen
dc.subject.lcshMetal oxide semiconductor field-effect transistorsen
dc.titleVoltage and temperature dependent gate capacitance and current model for high-K gate dielectric stacken
dc.type.genreThesisen

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