Design of low-power area-efficient continuous-time [delta-sigma] ADC using VCO-based integrators with intrinsic CLA

Simple item page
dc.contributor.advisorSun, Nan
dc.creatorLee, Kyoungtaeen
dc.date.accessioned2014-07-22T14:15:25Zen
dc.date.accessioned2018-01-22T22:26:21Z
dc.date.available2018-01-22T22:26:21Z
dc.date.issued2013-05en
dc.date.submittedMay 2013en
dc.date.updated2014-07-22T14:15:26Zen
dc.descriptiontexten
dc.description.abstractIn this thesis, the design of a scaling-friendly continuous-time closed-loop voltage controlled oscillator (VCO) based Delta-Sigma analog to digital converter (ADC) is introduced. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly operational transconductance amplifiers (OTAs) and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses digital to analog converter (DAC) mismatches. The prototype ADC in 130 nm complementary metal-oxide-semiconductor (CMOS) occupies a small area of 0.03 mm² and achieves 66.5 dB signal to noise and distortion ratio (SNDR) over 2 MHz bandwidth (BW) while sampling at 300 MHz and consuming 1.8 mW under a 1.2 V power supply. It can also operate with a low analog supply of 0.7 V and achieves 65.8 dB SNDR while consuming 1.1 mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25 pJ/conversion-step and 0.17 pJ/conversion-step, respectively.en
dc.description.departmentElectrical and Computer Engineeringen
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/2152/25258en
dc.subjectDelta-sigma ADCen
dc.subjectVCO-baseden
dc.titleDesign of low-power area-efficient continuous-time [delta-sigma] ADC using VCO-based integrators with intrinsic CLAen
dc.typeThesisen

Files

Collections

University of Texas at Austin