Simulation And E-beam Patterning Of Single Electron Transistor
| dc.contributor | Deep, Karan | en_US |
| dc.date.accessioned | 2007-08-23T01:56:00Z | |
| dc.date.accessioned | 2011-08-24T21:39:40Z | |
| dc.date.available | 2007-08-23T01:56:00Z | |
| dc.date.available | 2011-08-24T21:39:40Z | |
| dc.date.issued | 2007-08-23T01:56:00Z | |
| dc.date.submitted | November 2006 | en_US |
| dc.description.abstract | Electron beam lithography is gaining widespread use as semiconductor industry. Current optical lithography techniques are limited to resolution of few hundreds of nanometers and suffer from diffraction problems. The focus of this thesis is to pattern single electron transistors (SET) using electron beam lithography on silicon and silicon on insulator (SOI) substrate which can be further processed to form working SET device. We used different types of e-beam resists like UVN 30, PMMA and HSQ to define source, drain and island for SET. We demonstrated the use of RIE and Deep RIE to etch silicon by using resist as etch mask. Single electron transistor is simulated using a MATLAB program. This program calculates the current through SET as a function of drain-source voltage, VDS, for a given values of gate voltage Vg, which is predefined in the program. Simulations are performed at various temperatures from 4.2K and 77K. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10106/63 | |
| dc.language.iso | EN | en_US |
| dc.publisher | Electrical Engineering | en_US |
| dc.title | Simulation And E-beam Patterning Of Single Electron Transistor | en_US |
| dc.type | M.S.E.E. | en_US |