Synchrophasor Measurement Using Substation Intelligent Electronic Devices: Algorithms and Test Methodology



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This dissertation studies the performance of synchrophasor measurement obtained using substation Intelligent Electronic Devices (IEDs) and proposes new algorithms and test methodology to improve and verify their performance when used in power system applications.

To improve the dynamic performance when exposed to sinusoidal waveform distortions, such as modulation, frequency drift, abrupt change in magnitude, etc, an adaptive approach for accurately estimating phasors while eliminating the effect of various transient disturbances on voltages and currents is proposed. The algorithm pre-analyzes the waveform spanning the window of observation to identify and localize the discontinuities which affect the accuracy of phasor computation. A quadratic polynomial signal model is used to improve the accuracy of phasor estimates during power oscillations. Extensive experimental results demonstrate the advantages. This algorithm can also be used as reference algorithm for testing the performance of the devices extracting synchronized phasor measurements.

A novel approach for estimating the phasor parameters, namely frequency, magnitude and angle in real time based on a newly constructed recursive wavelet transform is developed. This algorithm is capable of estimating the phasor parameters in a quarter cycle of an input signal. It features fast response and achieves high accuracy over a wide range of frequency deviations. The signal sampling rate and data window size can be selected to meet desirable application requirements, such as fast response, high accuracy and low computational burden. In addition, an approach for eliminating a decaying DC component, which has significant impact on estimating phasors, is proposed using recursive wavelet transform.

This dissertation develops test methodology and tools for evaluating the conformance to standard-define performance for synchrophasor measurements. An interleaving technique applied on output phasors can equivalently increase the reporting rate and can precisely depict the transient behavior of a synchrophasor unit under the step input. A reference phasor estimator is developed and implemented. Various types of Phasor Measurement Units (PMUs) and PMU-enabled IEDs (Intelligent Electronic Devices) and time synchronization options have been tested against the standards using the proposed algorithm. Test results demonstrate the effectiveness and advantages.