Scheduling on-chip networks
| dc.contributor.advisor | Aziz, Adnan | en |
| dc.creator | Wu, Xiang | en |
| dc.date.accessioned | 2009-10-23T16:22:57Z | en |
| dc.date.accessioned | 2017-05-11T22:19:43Z | |
| dc.date.available | 2009-10-23T16:22:57Z | en |
| dc.date.available | 2017-05-11T22:19:43Z | |
| dc.date.issued | 2009-08 | en |
| dc.description | text | en |
| dc.description.abstract | Networks-on-Chip (NoC) have been proposed to meet many challenges of modern Systems-on-Chip (SoC) design and manufacturing. At the architectural level, a clean separation of computation and communication helps integration and verification. Networking abstraction of the communication infrastructure also promotes reuse and fast development. But the benefit is most visible when it comes to circuit and physical design. Networks can be made sparse and regular and thus facilitate placement and route. It is also much easier to reach timing and power closure as NoC shield communication details away from complicating analysis. Last but not the least, networks are flexible at the design stage and adaptable post-silicon. Many techniques of tackling process variation and interconnect failure can be built upon NoC. However, when interconnects are time multiplexed in a NoC, the network’s performance will deteriorate if it is not scheduled properly. For a wide range of applications, the traffic on the network can be determined before run-time and offline scheduling offers guaranteed performance and enables simple design. We propose a synthesis flow that takes the data flow graph of the application and a network topology as inputs; and outputs an offline schedule that can be deployed directly to the NoC. We analyze the complexity of combinatorial problems that arise from this context and provide efficient heuristics when polynomial time algorithms are not available assuming P [not equal to] NP. Results on LDPC decoding and FFT designs are compared with previous ones. We further apply our findings to parallel shared memories (PSM) and formalize the PSM architecture and its scheduling problem. An efficient heuristic is derived from our algorithm for unbuffered networks. Another application exemplifies how the NoC can be reprogrammed after silicon is back from fab in order to avoid failed interconnects due to process variation. A simple statistical model is studied and the simulation result is rather interesting. We find out that high performance and yield are not always at conflict if we are able to change the network schedule based on silicon diagnosis. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier.uri | http://hdl.handle.net/2152/6633 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject | Networks-on-chip design | en |
| dc.subject | Systems-on-chip design | en |
| dc.subject | Network scheduling | en |
| dc.subject | Interconnects | en |
| dc.subject | Parallel shared memories | en |
| dc.subject | Network traffic matrix scheduling | en |
| dc.subject | NoC design | en |
| dc.subject | Scheduling networks-on-chip | en |
| dc.title | Scheduling on-chip networks | en |