Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter
| dc.contributor.advisor | Abraham, Jacob A. | en |
| dc.contributor.advisor | Yan, Shouli | en |
| dc.creator | Gan, Jianhua | en |
| dc.date.accessioned | 2008-08-28T21:27:30Z | en |
| dc.date.accessioned | 2017-05-11T22:15:46Z | |
| dc.date.available | 2008-08-28T21:27:30Z | en |
| dc.date.available | 2017-05-11T22:15:46Z | |
| dc.date.issued | 2003 | en |
| dc.description | text | en |
| dc.description.abstract | It is very challenging to build precise analog circuits in deep sub-micron and nanometer VLSI fabrication technology. Advanced calibration methods are crucial in designing high performance analog and mixed-signal VLSI circuits. We present a non-binary capacitor array calibration method for a high performance successive approximation analog-to-digital converter (ADC). We show that the capacitor weights are successively refinable under the Markov condition using the rate-distortion theory. Using the analogy to discrete memoryless channel with interference known to the encoder, we show that the interference will not limit the final calibration accuracy if the calibration algorithm adapts to the interference. The capacitor array calibration algorithm is based on a perceptron learning rule, originally developed for Artificial Intelligence applications. It takes advantage of the redundancy in the non-binary capacitor array and the noise in the system to generate the learning cases. We propose a mixed-signal micro-controller architecture to efficiently implement the capacitor array calibration algorithm. A non-binary capacitor array with 20 capacitors is used to design a 16-bit successive approximation ADC. We discuss the design and trade-off of each circuit block in the ADC. We model the thermal noise, flicker noise, power supply interference, charge leakage and harmonic distortion in MATLAB. The calibration is robust under the influence of these nonidealities. The capacitor weights are adaptively calibrated to match the physical capacitors with up to 22-bit accuracy. Capacitor matching is not a limiting factor to the accuracy. The calibration time is about 50 ms. The calibration algorithm can also be used in other mixed-signal circuits to relax the requirement on analog circuits. | |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier | b5680412x | en |
| dc.identifier.oclc | 56078854 | en |
| dc.identifier.proqst | 3119619 | en |
| dc.identifier.uri | http://hdl.handle.net/2152/591 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject.lcsh | Analog-to-digital converters | en |
| dc.subject.lcsh | Analog-to-digital converters--Calibration | en |
| dc.subject.lcsh | Capacitors | en |
| dc.title | Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter | en |
| dc.type.genre | Thesis | en |