Central processing unit built-in self-test and enhanced statistical defect analysis compression for static random access memory
| dc.creator | Francis, David A | |
| dc.date.accessioned | 2016-11-14T23:11:25Z | |
| dc.date.available | 2011-02-19T01:08:45Z | |
| dc.date.available | 2016-11-14T23:11:25Z | |
| dc.date.issued | 2003-08 | |
| dc.degree.department | Electrical and Computer Engineering | en_US |
| dc.description.abstract | The percentage of digital signal processors (DSPs) occupied by embedded static random access memory (SRAM) has increased drastically over the years. As a result, static memory has become a prime contributor to the overall failure rate of DSP devices. Central Processing Unit Built hi Self Test (CPUbist) was thus developed in an effort to create a more economical and efficient method to test and repair such memories. CPUbist utilizes the power and speed of the on-chip processor, and demonstrates adequate and flexible memory fault coverage without the sacrifice of increased test time. This test method was used to not only test and create repair solutions for failing embedded SRAM, but also to map and compress bit fail data before offloading to the tester. To keep test cost at a minimum, the CPUbist programs were executed on the very low cost tester (VLCT), and data transfers were kept to a minimum by compressing fail data before offloading. All results obtained from CPUbist were then correlated with data from Membist, so as to ensure proper operation and to determine its level of effectiveness. The results of the correlation revealed that CPUbist can effectively test and repair DSP memories, in most instances at a faster rate than Membist. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/2346/22673 | en_US |
| dc.language.iso | eng | |
| dc.publisher | Texas Tech University | en_US |
| dc.rights.availability | Unrestricted. | |
| dc.subject | Integrated circuits -- Fault tolerance | en_US |
| dc.subject | Random access memory -- Reliability | en_US |
| dc.subject | Random access memory -- Testing | en_US |
| dc.subject | Integrated circuits -- Defects | en_US |
| dc.subject | Semiconductor storage devices | en_US |
| dc.title | Central processing unit built-in self-test and enhanced statistical defect analysis compression for static random access memory | |
| dc.type | Thesis |