Clock Distribution Network Optimization by Sequential Quadratic Programing

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dc.contributorHu, Jiang
dc.creatorMekala, Venkata
dc.date.accessioned2010-07-15T00:16:28Z
dc.date.accessioned2010-07-23T21:47:14Z
dc.date.accessioned2017-04-07T19:57:21Z
dc.date.available2010-07-15T00:16:28Z
dc.date.available2010-07-23T21:47:14Z
dc.date.available2017-04-07T19:57:21Z
dc.date.created2010-05
dc.date.issued2010-07-14
dc.description.abstractClock mesh is widely used in microprocessor designs for achieving low clock skew and high process variation tolerance. Clock mesh optimization is a very diffcult problem to solve because it has a highly connected structure and requires accurate delay models which are computationally expensive. Existing methods on clock network optimization are either restricted to clock trees, which are easy to be separated into smaller problems, or naive heuristics based on crude delay models. A clock mesh sizing algorithm, which is aimed to minimize total mesh wire area with consideration of clock skew constraints, has been proposed in this research work. This algorithm is a systematic solution search through rigorous Sequential Quadratic Programming (SQP). The SQP is guided by an efficient adjoint sensitivity analysis which has near-SPICE(Simulation Program for Integrated Circuits Emphasis)-level accuracy and faster-than-SPICE speed. Experimental results on various benchmark circuits indicate that this algorithm leads to substantial wire area reduction while maintaining low clock skew in the clock mesh. The reduction in mesh area achieved is about 33%.
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7753
dc.language.isoeng
dc.subjectOptimization
dc.subjectClock Distribution Network
dc.subjectSequential Quadratic Programming
dc.titleClock Distribution Network Optimization by Sequential Quadratic Programing
dc.typeBook
dc.typeThesis

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