Analysis techniques for nanometer digital integrated circuits
| dc.contributor.advisor | Pan, David Z. | en |
| dc.creator | Ramalingam, Anand, 1979- | en |
| dc.date.accessioned | 2008-08-29T00:01:58Z | en |
| dc.date.accessioned | 2017-05-11T22:18:56Z | |
| dc.date.available | 2008-08-29T00:01:58Z | en |
| dc.date.available | 2017-05-11T22:18:56Z | |
| dc.date.issued | 2007-12 | en |
| dc.description.abstract | As technology has scaled into nanometer regime, manufacturing variations have emerged as a major limiter of performance (timing) in VLSI circuits. Issues related to timing are addressed in the first part of the dissertation. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under uncertainty such as manufacturing variations. In this dissertation, we propose an efficient sparse-matrix framework for a path-based SSTA. In addition to an efficient framework for doing timing analysis, to improve the accuracy of the timing analysis one needs to address the accuracy of: waveform modeling, and gate delay modeling. We propose a technique based on Singular Value Decomposition (SVD) that accurately models the waveform in a timing analyzer. To improve the gate delay modeling, we propose a closed form expression based on the centroid of power dissipation. This new metric is inspired by our key observation that the Sakurai-Newton (SN) delay metric can be viewed as the centroid of current. In addition to accurately analyzing the timing of a chip, improving timing is another major concern. One way to improve timing is to scale down the threshold voltage (Vth). But scaling down increases the subthreshold leakage current exponentially. Sleep transistors have been proposed to reduce leakage current while maintaining performance. We propose a path-based algorithm to size the sleep transistor to reduce leakage while maintaining the required performance. In the second part of dissertation we address power grid and thermal issues that arise due to the scaling of integrated circuits. In the case of power grid simulation, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The transistor is modeled as a switch in series with an RC and the switch itself is modeled behaviorally. This model allows more accurate prediction of voltage drop compared to the current source model. In the case of thermal simulation, we address the issue of ignoring the nonlinearity of thermal conductivity in silicon. We found that ignoring the nonlinearity of thermal conductivity may lead to a temperature profile that is off by 10° C. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier.oclc | 212129874 | en |
| dc.identifier.uri | http://hdl.handle.net/2152/3661 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject.lcsh | Integrated circuits--Very large scale integration--Design and construction | en |
| dc.subject.lcsh | Transistors--Power supply | en |
| dc.subject.lcsh | Integrated circuits--Very large scale integration--Thermal conductivity | en |
| dc.title | Analysis techniques for nanometer digital integrated circuits | en |
| dc.type.genre | Thesis | en |