Algorithms for an IIL transistor-level logic simulator
| dc.creator | Ramesh, Subramanian | |
| dc.date.accessioned | 2016-11-14T23:08:08Z | |
| dc.date.available | 2011-02-18T18:58:43Z | |
| dc.date.available | 2016-11-14T23:08:08Z | |
| dc.date.issued | 1986-05 | |
| dc.degree.department | Computer Science | en_US |
| dc.description.abstract | Logic Simulators play an important role in the VLSI design verification process. Integrated Injection Logic circuits have a topology which is different from that of other bipolar technologies such as TTL or ECL. Traditional logic simulators do the simulation at the logic gate level. If these simulators are to be used for IIL circuits, the IIL circuit will have to be converted to an equivalent "normal" form. The proposed work presented here follows a different approach: the circuit is simulated at a transistor level. For every transition that takes place, the time-delays are computed using a simple model. Parasitics and loading effects are included in the time-delay calculation. An existing three-valued simulation algorithm is modified to accommodate the time-delay calculations and the topology of IIL. Finally, the approximations used in the model are evaluated using detailed SPICE simulations. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/2346/8881 | en_US |
| dc.language.iso | eng | |
| dc.publisher | Texas Tech University | en_US |
| dc.rights.availability | Unrestricted. | |
| dc.subject | Algorithms | en_US |
| dc.subject | Integrated circuits -- Very large scale integration | en_US |
| dc.subject | Integrated injection logic | en_US |
| dc.title | Algorithms for an IIL transistor-level logic simulator | |
| dc.type | Thesis |