Design of a Wide Bandwidth Continuous-time Low-pass Sigma-delta Modulator

Simple item page
dc.contributorSilva-Martinez, Jose
dc.contributorKarsilayan, Aydin
dc.creatorChien, Cheng-Ming
dc.date.accessioned2012-02-14T22:20:53Z
dc.date.accessioned2012-02-16T16:18:57Z
dc.date.accessioned2017-04-07T19:59:29Z
dc.date.available2012-02-14T22:20:53Z
dc.date.available2012-02-16T16:18:57Z
dc.date.available2017-04-07T19:59:29Z
dc.date.created2011-12
dc.date.issued2012-02-14
dc.description.abstractThe emergence of bandwidth-intensive services has created a need for high speed and high resolution data converters. Towards this end, system level design of a continuous-time sigma-delta modulator achieving 11 bits resolution over 100 MHz signal bandwidth by using a feed-forward topology is presented. The system is first built in the Simulink environment in MATLAB. The building blocks in the loop filter are modeled with non-idealities, and specifications for these blocks are obtained by simulations. An operational transconductor amplifier (OTA) with 100 mS transconductance, 70 dB linearity, and 34.2 mW power dissipation is designed to be used in the loop filter. Simulation results indicate that the 5th order loop filter implemented in the feed-forward architecture in transistor level shows lower power consumption, 105 mW, compared to the loop filter implemented by feedback architecture, 152 mW.
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10690
dc.language.isoen_US
dc.subjectcontinuous-time
dc.subjectsigma-delta
dc.subjectanalog-to-digital converter
dc.titleDesign of a Wide Bandwidth Continuous-time Low-pass Sigma-delta Modulator
dc.typeThesis

Files

Collections

Texas A&M University at College Station