Accelerating path planning algorithms with high level synthesis tools and FPGAs.

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dc.contributor.advisorDuren, Russell Walker.
dc.contributor.authorTrower, John W.
dc.contributor.departmentElectrical and Computer Engineering.en_US
dc.contributor.schoolsBaylor University. Dept. of Electrical and Computer Engineering.en_US
dc.date.accessioned2013-05-15T18:59:32Z
dc.date.accessioned2017-04-07T19:34:41Z
dc.date.available2013-05-15T18:59:32Z
dc.date.available2017-04-07T19:34:41Z
dc.date.copyright2012-12
dc.date.issued2013-05-15
dc.description.abstractAccelerating path planning algorithms with field programmable gate arrays (FPGA) allows the designer to achieve significant performance increases over using a traditional central processing unit (CPU). Converting an algorithm to run on an FPGA is a complicated and time consuming process. This thesis develops and verifies a design framework that demonstrates how to design a path planning algorithm in a high level language, then convert the algorithm into hardware description languages using high level synthesis tools. This design framework will be used to demonstrate the acceleration of a genetic algorithm.en_US
dc.description.degreeM.S.E.C.E.en_US
dc.identifier.urihttp://hdl.handle.net/2104/8600
dc.language.isoen_USen_US
dc.publisheren
dc.rightsBaylor University theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. Contact librarywebmaster@baylor.edu for inquiries about permission.en_US
dc.rights.accessrightsWorldwide access.en_US
dc.rights.accessrightsAccess changed 5/21/14.
dc.subjectPath planning algorithms.en_US
dc.subjectField programmable gate arrays.en_US
dc.subjectFPGA.en_US
dc.subjectHigh level synthesis tools.en_US
dc.subjectConverting algorithms.en_US
dc.titleAccelerating path planning algorithms with high level synthesis tools and FPGAs.en_US
dc.typeThesisen_US

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