Text compression implementation using an incrementor decompressor

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dc.contributor.advisorTouba, Nur A.
dc.creatorGao, Xu, 1980-
dc.date.accessioned2017-02-10T22:02:42Z
dc.date.accessioned2018-01-22T22:31:37Z
dc.date.available2017-02-10T22:02:42Z
dc.date.available2018-01-22T22:31:37Z
dc.date.issued2007-08
dc.description.abstractThis thesis describes a test pattern compression scheme that reduces test time by using specific on-chip decompression hardware for updating the test vector. Using the proposed hardware to update the test vector improves the bottleneck of data throughput between the tester and the device under test (DUT). This thesis uses an incrementor and an adder method to implement test decompression and compares the results. These approaches provide faster test times on a linear scale while retaining flexibility of test desired by industry.en_US
dc.description.departmentElectrical and Computer Engineeringen_US
dc.format.mediumelectronicen_US
dc.identifierdoi:10.15781/T26W96F13
dc.identifier.urihttp://hdl.handle.net/2152/45635
dc.language.isoengen_US
dc.relation.ispartofUT Electronic Theses and Dissertationsen_US
dc.rightsCopyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en_US
dc.rights.restrictionRestricteden_US
dc.subjectTest pattern compression schemeen_US
dc.subjectChip decompression hardwareen_US
dc.subjectTest vectoren_US
dc.titleText compression implementation using an incrementor decompressoren_US
dc.typeThesisen_US
dc.type.genreThesisen_US

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