Memristor-based arithmetic units

Simple item page
dc.contributor.advisorSwartzlander, Earl E., Jr., 1945-
dc.contributor.committeeMemberJohn, Lizy
dc.contributor.committeeMemberSchulte, Michael
dc.contributor.committeeMemberTouba, Nur
dc.contributor.committeeMemberLee, Jack
dc.creatorGuckert, Lauren Elise
dc.creator.orcid0000-0002-0720-5661
dc.date.accessioned2017-04-18T14:15:57Z
dc.date.accessioned2018-01-22T22:32:03Z
dc.date.available2017-04-18T14:15:57Z
dc.date.available2018-01-22T22:32:03Z
dc.date.issued2016-12
dc.date.submittedDecember 2016
dc.date.updated2017-04-18T14:15:57Z
dc.description.abstractThe modern computer architecture community is continually pushing the limits of performance, speed, and efficiency. Recently, the ability to satisfy this endeavor with popular CMOS technology has proved difficult, and in many settings, impossible. The community has begun to explore alternatives to standard practices, researching new components such as nanoscale structures. Additional research has applied these new components and their characteristics to rethink the architecture of the latest technology, moving away from the Von Neumann architecture. A leading technology in this effort is the memristor. Memristors are a new class of circuit elements that have the ability to change their resistance value while retaining knowledge of their current and past resistances. Their small form factor, high density, and fast switching times have sparked research in their applications in modern memory hierarchies. However, their utility in arithmetic has been minimally explored. This dissertation describes the prior work in the exploration of memristor technology, fabrication, modeling, and application, followed by the completed research performed in the design and implementation of arithmetic units using memristors. Implementations of popular adders, multipliers, and dividers in the context of memristors are designed using four approaches: IMPLY, hybrid-CMOS, threshold gates, and MAD gates. Each of these approaches has different tradeoffs and benefits for memristor-based design. Although the first three approaches have been defined in prior work, MAD gates are a novel application for memristors proposed that offer lower power, area, and delay as compared to prior approaches. This work explores these benefits for arithmetic unit design. The details of each designs, simulation results, and analyses in terms of complexity and delay and power are presented. For arithmetic units which have been designed or presented in prior work, this research improves upon the design in each metric. Many of the designs are transformed and pipelined to leverage memristor characteristics and the various approaches rather than traditional CMOS and this is discussed in detail. Overall, the proposed designs offer significant improvements to traditional CMOS designs, motivating the effort to continue exploring memristors and their application to modern computer architecture design.
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdf
dc.identifierdoi:10.15781/T25Q4RR9P
dc.identifier.urihttp://hdl.handle.net/2152/46491
dc.language.isoen
dc.subjectMemristors
dc.subjectIMPLY
dc.subjectHybrid-CMOS
dc.subjectThreshold
dc.subjectMAD gates
dc.subjectLogic-in-memory
dc.subjectCrossbar memory
dc.titleMemristor-based arithmetic units
dc.typeThesis
dc.type.materialtext

Files

Collections

University of Texas at Austin