Design techniques for high intermediate frequency bandpass (sigma/delta) modulator.

dc.contributorJose, Silva M.
dc.creatorKode, Praveena
dc.date.accessioned2008-10-10T21:00:40Z
dc.date.accessioned2017-04-07T19:54:04Z
dc.date.available2008-10-10T21:00:40Z
dc.date.available2017-04-07T19:54:04Z
dc.date.created2008-08
dc.date.issued2008-10-10
dc.description.abstractThe focus of the present thesis is the circuit-level implementation of an excess loop delay compensation scheme which optimizes excess loop delay in Analog-to-Digital Converter(ADC) by using a programmable delay block and synchronizes the signal passing through Dynamic Element Matching block, used to mitigate mismatch effects of multi-bit Digital-to-Analog Converter(DAC). The proposed delay block has tuning range of T/10 to T/2 seconds, with a step size of T/30 seconds, where T is the time period (1.25 nanoseconds) of sampling signal (800 MHz) in high IF (200 MHz) Bandpass [sigma delta] ADC. The implementation details of the element rotation scheme used to calibrate the multi-bit DAC static error mismatch are also presented. Also presented is the design of high frequency highly linear Operational Transconductance Amplifier(OTA) targeted for continuous-time filters in a high resolution High Intermediate Frequency (200 MHz) Bandpass [sigma delta] ADC for Software Radio applications. Proposed OTA uses super source follower input stage to enhance its voltage-to-current conversion linearity. The design has been simulated using TSMC 0.18 ?m CMOS process. The OTA has small signal transconductance of 0.9 mA/V, IM3 below -79 dB (for 0.3 Vpp input), Signal-to-Noise Ratio of 82 dB and power consumption of 6.8 mW, when tested in unity gain configuration.
dc.identifier.urihttp://hdl.handle.net/1969.1/86025
dc.language.isoen_US
dc.publisherTexas A&M University
dc.subjectLOOP DELAY
dc.subjectOTA
dc.titleDesign techniques for high intermediate frequency bandpass (sigma/delta) modulator.
dc.typeBook
dc.typeThesis

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