Yield improvement for analog to digital converter test

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dc.contributor.committeeChairParten, Michael E.
dc.contributor.committeeMemberNutter, Brian
dc.contributor.committeeMemberGale, Richard O.
dc.creatorKamalapuri, Poorvaja
dc.date.accessioned2016-11-14T23:07:23Z
dc.date.available2012-06-01T14:16:14Z
dc.date.available2016-11-14T23:07:23Z
dc.date.issued2007-05
dc.degree.departmentElectrical and Computer Engineering
dc.description.abstractA yield of 99% is a very demanding yet achievable target in the semiconductor industry. High volumes and fierce competition call for constant yield management. Continual monitoring of trends and process improvements aim to achieve such high yields. This thesis outlines a systematic approach to problem solving intended to serve as a guide to diagnose and solve yield issues. It also helps identify dead-ends to make pragmatic decisions in view of return on investment. An example problem of yield loss of an Analog to Digital Converter test is discussed to illustrate the procedure. Further, the steps taken to bring its yield up to a satisfying figure are explained.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/2346/17931
dc.language.isoeng
dc.rights.availabilityUnrestricted.
dc.subjectAnalog-to-digital converter
dc.subjectProblem solving
dc.subjectYield
dc.titleYield improvement for analog to digital converter test
dc.typeThesis

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