A random jitter RMS measurement method using AND and OR operations
dc.contributor.advisor | Abraham, Jacob A. | en |
dc.contributor.committeeMember | Touba, Nur | en |
dc.creator | Lee, Jae Wook, 1972- | en |
dc.date.accessioned | 2010-09-21T17:37:45Z | en |
dc.date.accessioned | 2010-09-21T17:37:50Z | en |
dc.date.accessioned | 2017-05-11T22:20:14Z | |
dc.date.available | 2010-09-21T17:37:45Z | en |
dc.date.available | 2010-09-21T17:37:50Z | en |
dc.date.available | 2017-05-11T22:20:14Z | |
dc.date.issued | 2009-12 | en |
dc.date.submitted | December 2009 | en |
dc.date.updated | 2010-09-21T17:37:50Z | en |
dc.description | text | en |
dc.description.abstract | Jitter is defined as timing uncertainties of digital signals at their intended ideal positions in time. While it undermines valuable clock budget and limits the maximum clock frequency in I/O circuitry, it is one of the most difficult parameters to measure accurately due to the small value and randomness. This thesis proposes a random jitter RMS measurement method using AND and OR operations, which targets BIST applications. This thesis is organized as follows. Chapter 1 introduces the motivation of the proposed work. It includes a comparison between two major approaches to jitter measurement. Chapter 2 explains the proposed random jitter estimation method in detail. Chapter 3 describes circuit implementations with design considerations. Chapter 4 demonstrates estimation results from circuit level simulation runs. Chapter 5 discusses the source of error in the jitter estimation and concludes. | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.uri | http://hdl.handle.net/2152/ETD-UT-2009-12-646 | en |
dc.language.iso | eng | en |
dc.subject | Random jitter | en |
dc.subject | AND operation | en |
dc.subject | OR operation | en |
dc.subject | Measurement | en |
dc.title | A random jitter RMS measurement method using AND and OR operations | en |
dc.type.genre | thesis | en |