Process variation aware low power buffer design
| dc.contributor.advisor | Orshansky, Michael | en |
| dc.contributor.committeeMember | Mcdermott, Mark | en |
| dc.creator | Lok, Mario Chichun | en |
| dc.date.accessioned | 2010-10-26T21:09:38Z | en |
| dc.date.accessioned | 2010-10-26T21:09:44Z | en |
| dc.date.accessioned | 2017-05-11T22:20:29Z | |
| dc.date.available | 2010-10-26T21:09:38Z | en |
| dc.date.available | 2010-10-26T21:09:44Z | en |
| dc.date.available | 2017-05-11T22:20:29Z | |
| dc.date.issued | 2010-05 | en |
| dc.date.submitted | May 2010 | en |
| dc.date.updated | 2010-10-26T21:09:44Z | en |
| dc.description | text | en |
| dc.description.abstract | In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield. | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/2152/ETD-UT-2010-05-1167 | en |
| dc.language.iso | eng | en |
| dc.subject | Low power design | en |
| dc.subject | Adaptive circuit | en |
| dc.subject | Statistical sizing | en |
| dc.subject | Tunable circuit | en |
| dc.subject | Adaptable optimization | en |
| dc.title | Process variation aware low power buffer design | en |
| dc.type.genre | thesis | en |