Discrete gate sizing and threshold voltage assignment to optimize power under performance constraints
| dc.contributor.advisor | Pan, David Z. | |
| dc.creator | Singh, Jagmohan | en |
| dc.date.accessioned | 2013-10-25T14:20:29Z | en |
| dc.date.accessioned | 2017-05-11T22:35:09Z | |
| dc.date.available | 2013-10-25T14:20:29Z | en |
| dc.date.available | 2017-05-11T22:35:09Z | |
| dc.date.issued | 2013-08 | en |
| dc.date.submitted | August 2013 | en |
| dc.description | text | en |
| dc.description.abstract | In today's world, it is becoming increasingly important to be able to design high performance integrated circuits (ICs) and have them run at as low power as possible. Gate sizing and threshold voltage (Vt) assignment optimizations are one of the major contributors to such trade-offs for power and performance of ICs. In fact, the ever increasing design sizes and more aggressive timing requirements make gate sizing and Vt assignment one of the most important CAD problems in physical synthesis. A promising gate sizing optimization algorithm has to satisfy requirements like being scalable to tackle very large design sizes, being able to optimally utilize a large (but finite) number of possible gate configurations available in standard cell library based on different gate sizes and/or threshold voltages (Vt) and/or gate lengths (Lg), and also, being able to handle non-convex cell delays in modern cell libraries. The work in this thesis makes use of the research-oriented infrastructure made available as part of the ISPD (International Symposium on Physical Design) 2012 Gate Sizing Contest that addresses the issues encountered in modern gate sizing problems. We present a two-phase optimization approach where Lagrangian Relaxation is used to formulate the optimization problem. In the first phase, the Lagrangian relaxed subproblem is iteratively solved using a greedy algorithm, while in the second phase, a cell downsizing and Vt upscaling heuristic is employed to further recover power from the timing-feasible and power-optimized sizing solution obtained at the end of first phase. We also propose a multi-core implementation of the first-phase optimizations, which constitute majority of the total runtime, to take advantage of multi-core processors available today. A speedup of the order of 4 to 9 times is seen on different benchmarks as compared to serial implementation when run on a 2 socket 6-core machine. Compared to the winner of ISPD 2012 contest, we further reduce leakage power by 17.21% and runtime by 87.92%, on average, while obtaining feasible sizing solutions on all the benchmark designs. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier.uri | http://hdl.handle.net/2152/21755 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject | Discrete gate sizing | en |
| dc.subject | Timing-constrained power optimization | en |
| dc.subject | Discrete optimization | en |
| dc.subject | Lagrangian relaxation | en |
| dc.subject | Computer-aided design | en |
| dc.title | Discrete gate sizing and threshold voltage assignment to optimize power under performance constraints | en |
| dc.type | Thesis | en |