Automating transformations from floating-point to fixed-point for implementing digital signal processing algorithms
dc.contributor.advisor | Evans, Brian L. (Brian Lawrence), 1965- | en |
dc.creator | Han, Kyungtae | en |
dc.date.accessioned | 2008-08-28T23:03:46Z | en |
dc.date.available | 2008-08-28T23:03:46Z | en |
dc.date.issued | 2006 | en |
dc.description | text | en |
dc.description.abstract | Many digital signal processing and communication algorithms are first simulated using floating-point arithmetic and later transformed into fixedpoint arithmetic to reduce implementation complexity. This transformation process may take more than 50% of the design time for complex designs. In addition, wordlengths in fixed-point designs may be altered at later stages in the design cycle. Different choices of wordlengths lead to different tradeoffs between signal quality and implementation complexity. In this dissertation, I propose two methods for characterizing the tradeoffs between signal quality and implementation complexity during the transformation of digital system designs to fixed-point arithmetic and variables. The first method, a gradient-based search for single-objective optimization with sensitivity information, scales linearly with the number of variables, but can become trapped in local optima. Based on wordlength design case studies for a wireless communication demodulator, adding sensitivity information reduces the search time by a factor of four and yields a design with 30% lower implementation costs. The second method, a genetic algorithm for multi-objective optimization, provides a Pareto optimal front that evolves towards the optimal tradeoff curve for signal quality vs. implementation complexity. This second method can be used to fully characterize the design space. I propose to use wordlength reduction methods of signed right shift and truncation to reduce power consumption in a given hardware architecture. For each method, I derive the expected values of the number of gates that switch during multiplication of the inputs. I apply the signed right shift method and the truncation method to a 16-bit radix-4 modified Booth multiplier and a 16- bit Wallace multiplier. The truncation method with 8-bit operands reduces the power consumption by 56% in the Wallace multiplier and 31% in the Booth multiplier. The signed right shift method shows a 25% power reduction in the Booth multiplier, but no power reduction in the Wallace multiplier. Finally, this dissertation describes a method to automate design assistance for transformation from floating-point to fixed-point data types. Floatingpoint programs are converted to fixed-point programs by a code generator. Then, the proposed wordlength search algorithms offer designers the freedom to determine data wordlengths to optimize the tradeoffs between signal quality and implementation complexity. | |
dc.description.department | Electrical and Computer Engineering | en |
dc.format.medium | electronic | en |
dc.identifier | b65008005 | en |
dc.identifier.oclc | 123348590 | en |
dc.identifier.uri | http://hdl.handle.net/2152/2702 | en |
dc.language.iso | eng | en |
dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
dc.subject.lcsh | Signal processing--Digital techniques | en |
dc.subject.lcsh | Algorithms | en |
dc.title | Automating transformations from floating-point to fixed-point for implementing digital signal processing algorithms | en |
dc.type.genre | Thesis | en |