Testing for delay defects utilizing test data compression techniques
| dc.contributor.advisor | Touba, Nur A. | en |
| dc.creator | Putman, Richard Dean, 1970- | en |
| dc.date.accessioned | 2008-08-29T00:19:55Z | en |
| dc.date.accessioned | 2017-05-11T22:19:28Z | |
| dc.date.available | 2008-08-29T00:19:55Z | en |
| dc.date.available | 2017-05-11T22:19:28Z | |
| dc.date.issued | 2008-05 | en |
| dc.description | text | en |
| dc.description.abstract | As technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways. | en |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier | b70674437 | en |
| dc.identifier.oclc | 244005082 | en |
| dc.identifier.uri | http://hdl.handle.net/2152/3922 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.subject.lcsh | Computers--Circuits--Testing | en |
| dc.subject.lcsh | Microelectromechanical systems--Design and construction | en |
| dc.subject.lcsh | Data compression (Computer science)--Testing | en |
| dc.title | Testing for delay defects utilizing test data compression techniques | en |
| dc.type.genre | Thesis | en |