Minimum supply voltage outlier analysis of large scale CMOS devices

Simple item page
dc.creatorMcDonald, David
dc.date.accessioned2016-11-14T23:18:16Z
dc.date.available2011-02-18T21:02:27Z
dc.date.available2016-11-14T23:18:16Z
dc.date.issued2004-05
dc.degree.departmentElectrical and Computer Engineeringen_US
dc.description.abstractThe theory and experiment of low voltage testing outlier screening methods will be proposed in this paper. Including an active study of maximum operating frequencies in comparison to their minimum voltage operating conditions. The objective of this paper is to discuss the possibility of using low voltage testing and outlier screening methods to reduce bum in time of large scale Integrated Circuits (IC's). In today's ever growing semiconductor market the need for test time reduction and test cost is ever present. By decreasing test overhead a company has the ability to lower product cost and manufacturing time and at the same time increasing potential profit and revenue.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/2346/15312en_US
dc.language.isoeng
dc.publisherTexas Tech Universityen_US
dc.rights.availabilityUnrestricted.
dc.subjectHigh voltages -- Measurementen_US
dc.subjectSemiconductorsen_US
dc.subjectLogic circuitsen_US
dc.subjectLow voltage integrated circuitsen_US
dc.subjectBreakdown voltageen_US
dc.subjectElectronic instrumentsen_US
dc.titleMinimum supply voltage outlier analysis of large scale CMOS devices
dc.typeThesis

Files

Collections

Texas Tech University