Statistical static timing analysis considering the impact of power supply noise in VLSI circuits

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dc.contributorWalker, Duncan M. H.
dc.creatorKim, Hyun Sung
dc.date.accessioned2010-01-15T00:13:58Z
dc.date.accessioned2010-01-16T02:20:24Z
dc.date.accessioned2017-04-07T19:56:51Z
dc.date.available2010-01-15T00:13:58Z
dc.date.available2010-01-16T02:20:24Z
dc.date.available2017-04-07T19:56:51Z
dc.date.created2007-08
dc.date.issued2009-06-02
dc.description.abstractAs semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology. In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated. Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-1902
dc.language.isoen_US
dc.subjectStatistical Static Timing Analysis
dc.subjectpower supply noise
dc.titleStatistical static timing analysis considering the impact of power supply noise in VLSI circuits
dc.typeBook
dc.typeThesis

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