A dual-loop frequency synthesizer



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A dual-loop frequency synthesizer is proposed to reduce the phase noise introduced by the Voltage Controlled Oscillator (VCO) which is the main source of noise in a traditional PLL based frequency synthesizer. The focus of this thesis is on the analysis and simulation of the proposed dual-loop frequency synthesizer architecture and comparison of results with that of the standard frequency synthesizer. Instead of the traditional PLL based frequency synthesizer with single feedback loop from the VCO output through a divider back to the phase detector an additional feedback path from VCO output through a Frequency to Voltage Converter (FVC) to the input of the loop filter is introduced. Results show considerable improvement in the phase noise performance and the lock time. The improved performance can be attributed to noise suppression in the loop for reasons similar to a sigma-delta modulator. Due to this improved noise performance dual-loop frequency synthesizer is suitable for applications which require high phase noise suppression.