Improving the Simulation Environment for Computer Architecture
| dc.contributor | Gratz, Paul V. | |
| dc.creator | Naranjo Carmona, Alberto Javier | |
| dc.date.accessioned | 2015-04-28T15:36:32Z | |
| dc.date.accessioned | 2017-04-07T20:15:45Z | |
| dc.date.available | 2015-04-28T15:36:32Z | |
| dc.date.available | 2017-04-07T20:15:45Z | |
| dc.date.created | 2014-12 | |
| dc.date.issued | 2014-12-03 | |
| dc.description.abstract | This work presents the efforts to improve the simulation environment for computer architecture research through two major contributions: The addition of a three level cache hierarchy and implementation of a statistical sampling simulation framework. Full-system and micro-architectural simulation are the primary and most reliable research tools that the computer architecture community has. However, keeping the simulator up to date with the latest industry products is a challenging task, causing a growing time gap between the release of new commercial products and the implementation of their models in the simulators. Another problem architects have to deal with is the performance gap; the time spent on simulating one instruction is several orders of magnitude bigger than the time the real hardware takes to execute the same instruction. This leads to prohibitively long simulation times that, due to the always efficiency-focused industry trend, is also to be increased. As processors get more complex, so do the simulators. The performance improvement achieved by real hardware changes is too small compared to the overhead induced into the simulator while trying to replicate those same changes. Although a third level (L3) cache hierarchy is a common feature in current processors and its benefits in performance have been known for decades, currently, it is not supported in most full-system simulators. A modern full system simulator was extended to include a third level cache and experiments show that for the PARSEC benchmarks, the performance of the system with L3 is ? 30% better than the baseline. On the other hand the implementation of statistical sampling simulation allows a greater improvement in simulation performance while statistics theory guarantees that the subset of instructions executed are a representative sample of the benchmark behaviour. The experiments show a measured CPI error of less than 2.5% while achieving simulation time speed-ups of around 3X. | |
| dc.identifier.uri | http://hdl.handle.net/1969.1/154153 | |
| dc.language.iso | en | |
| dc.subject | cache coherence | |
| dc.subject | coherence protocol | |
| dc.subject | sampling simulation | |
| dc.subject | simulation speed-up | |
| dc.title | Improving the Simulation Environment for Computer Architecture | |
| dc.type | Thesis |