Design, implementation, and measurements of a high speed serial link equalizer

dc.contributor.advisorAziz, Adnanen
dc.contributor.committeeMemberMcDermott, Marken
dc.creatorEvans, Andrew Johnen 2012en
dc.description.abstractThe advancements of semiconductor processing technology have led to the ability for computing platforms to operate on large amounts of data at very high clock speeds. To fully utilize this processing power the components must have data continually available for operation upon and transport to other system components. To enable this data requirement, high speed serial links have replaced slower parallel communication protocols. Serial interfaces inherently require fewer signals for communication and thus reduce the device pin count, area and cost. A serial communication interface can also be run at a higher frequency because the clock skew between channels is no longer an issue since the data transmitted on various channels is independent. Serial data transmission also comes with a set of drawbacks when signal integrity is considered. The data must propagate through a channel that induces unwanted effects onto the signals such as intersymbol interference. These channel effects must be understood and mitigated to successfully transmit data without creating bit errors upon reception at the target component. Previously developed adaptive equalization techniques have been used to filter the effects of intersymbol interference from the transmitted data in the signal. This report explores the modeling and implementation of a system comprised of a transmitter, channel, and receiver to understand how intersymbol interference can be removed through a decision-feedback equalizer realized in hardware. The equalizer design, implementation, and measurements are the main focus of this report and are based on previous works in the areas of integrated circuit testing, channel modeling, and equalizer design. Simulation results from a system modeled in Simulink are compared against the results from a hardware model implemented with an FPGA, analog to digital converter and discrete circuit elements. In both the software and hardware models, bit errors were eliminated for certain amounts of intersymbol interference when a receiver with decision-feedback equalization was used instead of a receiver without equalization.en
dc.description.departmentElectrical and Computer Engineeringen
dc.subjectDecision-feedback equalizeren
dc.subjectSerial linken
dc.subjectIntersymbol interferenceen
dc.titleDesign, implementation, and measurements of a high speed serial link equalizeren