Optimizing cycle time through SRAM repairs

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dc.contributor.committeeChairParten, Michael E.
dc.contributor.committeeMemberNutter, Brian
dc.contributor.committeeMemberCox, Ronald H.
dc.creatorPemberton, Lacey D.
dc.date.accessioned2016-11-14T23:26:00Z
dc.date.available2012-06-01T17:41:21Z
dc.date.available2016-11-14T23:26:00Z
dc.date.issued2006-12
dc.degree.departmentElectrical and Computer Engineering
dc.description.abstractThis thesis describes a project on large microprocessor integrated circuits using very large scale integration (VLSI) technologies. This project will serve to confirm the hypothesis that using large microprocessors with embedded static random access memory (SRAM) yield model results can filter devices that are predicted to fail at the final test due to the number of SRAM repairs. This model will help reduce cycle time.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/2346/17251
dc.language.isoeng
dc.rights.availabilityUnrestricted.
dc.subjectSRAM
dc.titleOptimizing cycle time through SRAM repairs
dc.typeThesis

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