Exploiting level sensitive latches in wire pipelining

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dc.contributorHu, Jiang
dc.creatorSeth, Vikram
dc.date.accessioned2005-02-17T21:01:22Z
dc.date.accessioned2017-04-07T19:49:30Z
dc.date.available2005-02-17T21:01:22Z
dc.date.available2017-04-07T19:49:30Z
dc.date.created2004-12
dc.date.issued2005-02-17
dc.description.abstractThe present research presents procedures for exploitation of level sensitive latches in wire pipelining. The user gives a Steiner tree, having a signal source and set of destination or sinks, and the location in rectangular plane, capacitive load and required arrival time at each of the destinations. The user also defines a library of non-clocked (buffer) elements and clocked elements (flip-flop and latch), also known as synchronous elements. The first procedure performs concurrent repeater and synchronous element insertion in a bottom-up manner to find the minimum latency that may be achieved between the source and the destinations. The second procedure takes additional input (required latency) for each destination, derived from previous procedure, and finds the repeater and synchronous element assignments for all internal nodes of the Steiner tree, which minimize overall area used. These procedures utilize the latency and area advantages of latch based pipelining over flip-flop based pipelining. The second procedure suggests two methods to tackle the challenges that exist in a latch based design. The deferred delay padding technique is introduced, which removes the short path violations for latches with minimal extra cost.
dc.identifier.urihttp://hdl.handle.net/1969.1/1433
dc.language.isoen_US
dc.publisherTexas A&M University
dc.subjectlatches
dc.subjectwire
dc.subjectpipelining
dc.subjectlatency
dc.subjectdelay
dc.subjectsignal
dc.titleExploiting level sensitive latches in wire pipelining
dc.typeBook
dc.typeThesis

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