Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic
| dc.contributor | Silva-Martinez, Jose | |
| dc.creator | Jeon, Hyung-Joon | |
| dc.date.accessioned | 2015-05-01T05:57:07Z | |
| dc.date.accessioned | 2017-04-07T20:03:52Z | |
| dc.date.available | 2015-05-01T05:57:07Z | |
| dc.date.available | 2017-04-07T20:03:52Z | |
| dc.date.created | 2013-05 | |
| dc.date.issued | 2013-03-19 | |
| dc.description.abstract | As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers? relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation. | |
| dc.identifier.uri | http://hdl.handle.net/1969.1/149205 | |
| dc.language.iso | en | |
| dc.subject | Integrated circuit | |
| dc.subject | Mixed signal | |
| dc.subject | Serial link | |
| dc.subject | Clock and Data Recovery | |
| dc.subject | CDR | |
| dc.subject | Current Mode Logic | |
| dc.subject | CML | |
| dc.subject | Phase Locked Loop | |
| dc.subject | PLL | |
| dc.title | Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic | |
| dc.type | Thesis |