Qualification of the assembly process of flip-chip BGA packages for the next generation synchronous quad data rate sram device to ensure reliability

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dc.contributor.committeeChairGale, Richard O.
dc.contributor.committeeChairBayne, Stephen B.
dc.creatorShivan, Nivetha
dc.date.accessioned2016-11-14T23:32:33Z
dc.date.available2012-06-28T19:39:17Z
dc.date.available2016-11-14T23:32:33Z
dc.date.issued2012-05
dc.degree.departmentElectrical and Computer Engineering
dc.description.abstractQuad Data Rate SRAMS (QDR SRAM) with a maximum speed of 550MHz are the latest technology QDRs in the market. These devices use the traditional wire-bonding interconnects ball grid array package technology with about 165 signal pins. There are next generation QDR SRAMS that are being designed which operates at speeds much higher than 550MHz and signal pins twice as much as that of the present QDRs. These new products would require a new packaging interconnect technology called Flip Chip in order to accommodate higher speed and increased number of signal pins. The reason for this is that Flip Chip shows improved electrical properties over wire-bonding technologies. In this thesis, we deal with the qualification of Flip Chip interconnects technology for a higher pin count device.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/2346/45324
dc.language.isoeng
dc.rights.availabilityUnrestricted.
dc.subjectComputer storage devices
dc.subjectRandom access memory
dc.subjectFlip chip technology
dc.titleQualification of the assembly process of flip-chip BGA packages for the next generation synchronous quad data rate sram device to ensure reliability
dc.typeThesis

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