Gate dielectrics on strained SiGe
| dc.contributor.advisor | Banerjee, Sanjay | en |
| dc.creator | Ngai, Tat | en |
| dc.date.accessioned | 2011-06-10T20:59:44Z | en |
| dc.date.available | 2011-06-10T20:59:44Z | en |
| dc.date.issued | 2002-12 | en |
| dc.description | text | en |
| dc.description.abstract | Buried channel SiGe PMOSFET performance is degraded by the requirement of Si caps. However, fabrication of surface channel SiGe PMOSFETs has rarely been successful due to gate oxide problems. Low temperature deposited SiO2 using remote plasma CVD (RPCVD) and high-k gate dielectric ZrO2 using DC magnetron reactive sputtering have been investigated for SiGe applications in this work. A low temperature gate quality silicon dioxide process has been developed using Remote Plasma Chemical Vapor Deposition (RPCVD). By carefully controlling the background water concentration, a high quality SiO2/Si interface can be achieved even without the pre-oxidation. RPCVD oxide films deposited on Si have excellent as-deposited interfacial (Dit ~ 1x1010 cm -2eV-1) and bulk (Ebd > 10 MV/ cm) electrical properties. However, SiGe MOSFETs with high quality RPCVD SiO2 still under-perform Si devices because of a poor interface. Low temperature water vapor annealing seems to be very effective to passivate the dangling bonds at the SiO2/SiGe interface. More than 20% transconductance improvement is observed in SiGe devices after water vapor annealing. This dissertation also reports the electrical properties of a high-k material, ZrO2, deposited directly on SiGe, without the use of a Si cap layer or a passivation barrier. ZrO2 thin films of equivalent oxide thickness (EOT) down to 16.5 Å were deposited on strained SiGe layers by reactive sputtering. Results indicate that ZrO2 films on SiGe have good interfacial properties and low leakage currents. Silicon and surface channel SiGe PMOSFETs using a ZrO2 gate dielectric with EOT less than 20 Å was fabricated. Mobility enhancement is also observed in SiGe devices. ZrO2 shows great promise as an alternative gate dielectric for SiGe applications. | |
| dc.description.department | Electrical and Computer Engineering | en |
| dc.format.medium | electronic | en |
| dc.identifier.uri | http://hdl.handle.net/2152/11646 | en |
| dc.language.iso | eng | en |
| dc.rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. | en |
| dc.rights.restriction | Restricted | en |
| dc.subject | Gate array circuits | en |
| dc.subject | Dielectrics | en |
| dc.subject | Silicon compounds | en |
| dc.subject | Germanium compounds | en |
| dc.title | Gate dielectrics on strained SiGe | en |