New methodology for low power and less test time in VLSI testing

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dc.contributor.advisorAmbler, Anthony P.en
dc.creatorLee, Il-Sooen
dc.date.accessioned2008-08-28T22:55:28Zen
dc.date.accessioned2017-05-11T22:17:19Z
dc.date.available2008-08-28T22:55:28Zen
dc.date.available2017-05-11T22:17:19Z
dc.date.issued2006en
dc.descriptiontexten
dc.description.departmentElectrical and Computer Engineeringen
dc.format.mediumelectronicen
dc.identifierb64813800en
dc.identifier.oclc82368421en
dc.identifier.urihttp://hdl.handle.net/2152/2561en
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subject.lcshIntegrated circuits--Very large scale integration--Testingen
dc.subject.lcshIntegrated circuits--Testingen
dc.titleNew methodology for low power and less test time in VLSI testingen
dc.type.genreThesisen

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