Characterication of wire delays in large SRAM arrays

As the size of on-chip caches in continues to increase, wire delays become a more dominant factor in limiting the speed of the cache. The fact that the wire length for each bit in the array is different causes a significant speed delta between the fastest and slowest bits in a given array. The speed difference between the fastest and slowest bit cells causes a reliability concern if the entire array is tested at a single speed. This paper will quantify the speed difference between the fastest and slowest bits in the L2 cache of the Ultrasparc IV processor, and examine the possible reliability impacts of this difference.