Charge trapping effects on mobility and threshold voltage instability in high-k gate stacks
Sim, Jang Hoan
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In order to provide better performance and higher packing density on the limited space, scaling down of the channel length is essential in ULSI fabrication technologies. Although the thermally grown or rapid thermally grown oxynitride with EOT of 18~25Å has been introduced in the manufacturing area for the replacement of SiO2 to further scale technology, the technology for beyond 0.1Pm still needs further thickness scaling of SiO2 or oxynitride and is approaching the scaling limits. Therefore, new materials such as high-k dielectrics and metal gate electrodes have been investigated in order to ensure continued scaling of the technology. Among multiple candidates such as Ta2O5, TiO2, Al2O3, Y2O3, La2O3, ZrO2, the HfO2-based material has been presently considered the most attractive candidate for the gate dielectric application due to its high k value, better device performance and thermal stability, etc. However, various challenges for high-k devices implemetation include low mobility and threshold voltage instability, which can be affected by the quality of the interfacial oxide and charge trapping. In particular, transient charge trapping was proposed to be one of the main resources for mobility reduction. Even though several process modifications, such as nitridation and silicate formation, suggest the ways for improvement of high-k dielectrics device performance, the effect of these changes has not been yet studied systematically. The reliability issues of the hafnium-based dielectrics, such as TDDB, bias temperature instabilities, and hot carrier stability, needs to be addressed in order to introduce high-k technology in 45 nm technology node. In this work, charge trapping effects on channel carrier mobility with metal gate electrode are investigated. ALD (Atomic Layer Deposition) process can improve uniformity of high-k layer. Channel carrier mobility of the HfO2 dielectric is shown be to underestimated by the impact of fast transient electron trapping during D.C. measurements. By reducing transient charging, effective mobility, as well as performance in general, of the high-k transistors can be improved. Scaling the physical thickness of the HfO2 dielectric was demonstrated to result in less charge trapping and higher mobility. We have introduce a localized transient charging model, which indicates that a portion of the hot carrier stress (HCS) degradation is due to the cold channel carrier injection rather than hot carrier injection. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier trapping induces permanent damage of the dielectric while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.