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dc.contributorHu, Jiang
dc.creatorHenrichson, Trenton D.
dc.date.accessioned2010-01-14T23:54:13Z
dc.date.accessioned2010-01-16T02:30:16Z
dc.date.accessioned2017-04-07T19:56:59Z
dc.date.available2010-01-14T23:54:13Z
dc.date.available2010-01-16T02:30:16Z
dc.date.available2017-04-07T19:56:59Z
dc.date.created2008-12
dc.date.issued2010-01-14
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100
dc.description.abstractTransistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging. Using HSPICE and 70nm BPTM process numbers, we simulated the technique on four circuits (a ring oscillator, a fan-out four circuit, an ISCAS c432 and c2670). Over the lifetime of the circuit, our simulations predict a 8.89% and a 13% improvement in power in the c432 and c2670 circuits respectively when compared to similarly performing traditional circuits.
dc.language.isoen_US
dc.subjectTransistor Ageing Antifuse NBTI negative bias temperature instability FTS Field Transistor Sizing
dc.titleCountering Aging Effects through Field Gate Sizing
dc.typeBook
dc.typeThesis


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